Lg 42pa4500-um 42pa450c-um Chassis Pu23a 2f495q

Internal Use Only North/Latin America Europe/Africa Asia/Oceania

http://aic.lgservice.com http://eic.lgservice.com http://biz.lgservice.com

PLASMA TV SERVICE MANUAL CHASSIS : PU23A

MODEL : 42PA4500 MODEL : 42PA450C

CAUTION

42PA4500-UM 42PA450C-UM

BEFORE SERVICING THE CHASSIS, READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

P/NO : MFL67564901 (1205-REV00)

Printed in Korea

CONTENTS

CONTENTS . ............................................................................................. 2 SAFETY PRECAUTIONS ......................................................................... 3 SPECIFICATION........................................................................................ 4 ADJUSTMENT INSTRUCTION................................................................. 5 BLOCK DIAGRAM................................................................................... 12 EXPLODED VIEW .................................................................................. 13 SCHEMATIC CIRCUIT DIAGRAM ..............................................................

Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes

-2-

LGE Internal Use Only

SAFETY PRECAUTIONS IMPORTANT SAFETY NOTICE Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and Exploded View. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.

General Guidance

Leakage Current Hot Check (See below Figure) Plug the AC cord directly into the AC outlet.

An isolation Transformer should always be used during the servicing of a receiver whose chassis is not isolated from the AC power line. Use a transformer of adequate power rating as this protects the technician from accidents resulting in personal injury from electrical shocks. It will also protect the receiver and it's components from being damaged by accidental shorts of the circuitry that may be inadvertently introduced during the service operation. If any fuse (or Fusible Resistor) in this TV receiver is blown, replace it with the specified. When replacing a high wattage resistor (Oxide Metal Film Resistor, over 1 W), keep the resistor 10 mm away from PCB. Keep wires away from high voltage or high temperature parts.

Do not use a line Isolation Transformer during this check. Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor between a known good earth ground (Water Pipe, Conduit, etc.) and the exposed metallic parts. Measure the AC voltage across the resistor using AC voltmeter with 1000 ohms/volt or more sensitivity. Reverse plug the AC cord into the AC outlet and repeat AC voltage measurements for each exposed metallic part. Any voltage measured must not exceed 0.75 volt RMS which is corresponds to 0.5 mA. In case any measurement is out of the limits specified, there is possibility of shock hazard and the set must be checked and repaired before it is returned to the customer.

Leakage Current Hot Check circuit

AC Volt-meter

Before returning the receiver to the customer, always perform an AC leakage current check on the exposed metallic parts of the cabinet, such as antennas, terminals, etc., to be sure the set is safe to operate without damage of electrical shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an electrical jumper across the two AC plug prongs. Place the AC switch in the on position, connect one lead of ohm-meter to the AC plug prongs tied together and touch other ohm-meter lead in turn to each exposed metallic parts such as antenna terminals, phone jacks, etc. If the exposed metallic part has a return path to the chassis, the measured resistance should be between 1 MΩ and 5.2 MΩ. When the exposed metal has no return path to the chassis the reading must be infinite. An other abnormality exists that must be corrected before the receiver is returned to the customer.

Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes

-3-

To Instrument's exposed METALLIC PARTS

Good Earth Ground such as WATER PIPE, CONDUIT etc.

LGE Internal Use Only

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement.

1. Application range

This spec sheet is applied all of the PDP TV with PU23A chassis.

2. Requirement for Test

Each part is tested as below without special appointment. (1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C (2) Relative Humidity: 65 % ± 10 % (3) Power Voltage : Standard input voltage (AC 100-240 V~, 50/60 Hz) * Standard Voltage of each products is marked by models. (4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with BOM. (5) The receiver must be operated for about 5 minutes prior to the adjustment.

3. Test method

(1) Performance: LGE TV test method followed (2) Demanded other specification - Safety : CE, IEC specification - EMC : CE, IEC

4. Model General Specification No

Item

Specification

1

Receiving System

1) ATSC / NTSC-M

2

Available Channel

1) VHF : 02~13 2) UHF : 14~69 3) DTV : 02-69 4) CATV : 01~135 5) CADTV : 01~135

3

Input Voltage

1) AC 100 ~ 240V 50/60Hz

4

Market

NORTH AMERICA

5

Screen Size

42 inch Wide(1024 × 768) 50 inch Wide(1024 × 768) 50 inch Wide(1920 × 1080) 60 inch Wide(1920 × 1080)

6

Aspect Ratio

16:9

7

Tuning System

FS

8

Module

PDP42T4#### PDP50T4#### PDP50R4#### PDP60R4####

9

Operating Environment

1) Temp : 0 ~ 40 deg 2) Humidity : ~ 80 %

10

Storage Environment

1) Temp : -20 ~ 60 deg 2) Humidity : ~ 85 %

Remark

42PA all model 50PA all model 50PA all model 60PA all model

(1024 × 768) (1024 × 768) (1920 × 1080) (1920 × 1080)

Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes

42PA all model 50PA all model 50PA all model 60PA all model

-4-

LGE Internal Use Only

ADJUSTMENT INSTRUCTION 1. Application Range

This spec. sheet applies to PU23A chassis applied PDP TV all models manufactured in TV factory.

4. PCB Assembly Adjustment 4.1. Using RS-232C

2. Specification

- A djust 3 items at 3.1. PCB assembly adjustments " 4.1. ■ Adjustment sequence" one after the order. ■ Adjustment sequence

(1) Because this is not a hot chassis, it is not necessary to use an isolation transformer. However, the use of isolation transformer will help protect test instrument. (2) Adjustment must be done in the correct order. But it is flexible when its factory local problem occurs. (3) The adjustment must be performed in the circumstance of 25 °C ± 5 °C of temperature and 65 % ± 10 % of relative humidity if there is no specific designation. (4) The input voltage of the receiver must keep AC 100-240 V~, 50/60 Hz. (5) Before adjustment, execute Heat-Run for 5 minutes.

Order

command

Set response

1. Inter the Adjustment mode

aa 00 00

a 00 OK00x

2. C hange the Source

XB 00 40 XB 00 60

b 00 OK40x (Adjust 480i Comp1 ) (Adjust 1080p Comp1) b 00 OK60x (Adjust 1080p RGB)

3. Start Adjustment

ad 00 10

4. R eturn the Response

OKx ( Success condition ) NGx ( Failed condition )

■ A fter Receive 100% Full white pattern (06CH) then process Heat-run (or “8. Test pattern” condition of Ez-Adjust status)

5. R ead Adjustment data

( main ) ad 00 20 ( main ) ad 00 30

(main : component1 480i, RGB 1080p) 000000000000000000000000007c007b006dx (main : component1 1080p) 000000070000000000000000007c00830077x

■ How to make set white pattern 1) Press Power ON button of Service Remocon 2) Press ADJ button of Service remocon. Select “10. Test pattern” and, after select “White” using navigation button, and then you can see 100% Full White pattern.

6. Confirm Adjustment

ad 00 99

NG 03 00x (Failed condition) NG 03 01x (Failed condition) NG 03 02x (Failed condition) OK 03 03x (Success condition)

7. End of Adjustment

ad 00 90

d 00 OK90x

* In this status you can maintain Heat-Run useless any pattern generator * Notice: if you maintain one picture over 20 minutes (Especially sharp distinction black with white pattern – 13Ch, or Cross hatch pattern – 09Ch) then it can appear image stick near black level.

3. Adjustment items

3.1. PCB Assembly adjustment

■ Adjust 480i Comp1 ■ Adjust 1080p Comp1/RGB ● If it is necessary, it can adjustment at Manufacture Line ● You can see set adjustment status at “9. ADJUST CHECK” of the “In-start menu”

3.2. Set Assembly Adjustment

■ EDID (The Extended Display Identification Data ) ■ Color Temperature (White Balance) Adjustment ■ Make sure RS-232C control ■ Selection Factory output option

Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes

-5-

< See ADC Adjustment RS232C Protocol_Ver1.0 > ■ Necessary items before Adjustment items ● Pattern Generator : (MSPG-925FA) ● Adjust 480i comp1 (MSPG-925FA:model :209, pattern :65) - comp1 Mode ● Adjust 1080p comp1 (MSPG-925FA:model :225 , pattern :65) - comp1 Mode ● Addjust RGB (MSPG-925FA:model :225 , pattern :65) - RGB-Pc Mode * If you want more information then see the below Adjustment method (Factory Adjustment) ■ Adjustment sequence ● aa 00 00: Enter the ADc Adjustment mode. ● xb 00 40: change the mode to component1 (No actions) ● ad 00 10: Adjust 480i comp ● ad 00 10: Adjust 1080p comp ● xb 00 60: change to RGB-Pc mode(No action) ● ad 00 10: Adjust 1080p RGB ● xb 00 90: Endo of Adjustmennt

LGE Internal Use Only

5. Factory Adjustment

-> PU23A : USE INTERNAL ADC(LM1) : using internal pattern.

5.1. Auto Adjust Component 480i/1080p RGB 1080p

■ Summary : A djustment component 480i/1080i and RGB 1080p is Gain and Black level setting at Analog to Digital converter, and compensate the RGB deviation ■ Using instrument ● A djustment remocon, 801GF(802B, 802F, 802R) or MSPG925FA pattern generator (I t can output 480i/1080i horizontal 100% color bar pattern signal, and its output level must setting 0.7V±0.1V p-p correctly)

* caution : Set Volume 0 after adjustment

5.2. Use Internal ADC(S7R)

- A DJ(EZ ADJUST) -> 6.ADC Calibration -> ADC Calibration(START)

< Adjustment pattern : 480i / 1080p 60Hz Pattern > ● You must make it sure its resolution and pattern cause every instrument can have different setting ● Adjustment method 480i Comp1, Adjust 1080p Comp1/ RGB (Factory adjustment) ● ADC 480i Component1 adjustment - Check connection of Component1 - MSPG-925FA -> Model: 209, Pattern 65 ● Set Component 480i mode and 100% Horizontal Color Bar Pattern(HozTV31Bar), then set TV set to Component1 mode and its screen to “NORMAL” ● ADC 1080p Component1 / RGB adjustment - Check connection both of Component1 and RGB - MSPG-925FA -> Model: 225, Pattern 65 ● Set Component 1080p mode and 100% Horizontal Color Bar Pattern(HozTV31Bar), then set TV set to Component1 mode and its screen to “NORMAL” ● After get each the signal, wait more a second and enter the “IN-START” with press IN-START key of Service remocon. After then select “7. External ADC” with navigator button and press “Enter”. ● After Then Press key of Service remocon “Right Arrow (VOL+)” ● You can see “ADC Component1 Success” ● Component1 1080p, RGB 1080p Adjust is same method. ● C omponent 1080p Adjustment in Component1 input mode ● RGB 1080p adjustment in RGB input mode ● If you success RGB 1080p Adjust. You can see “ADC RGB-DTV Success”

Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes

-6-

* E DID (The Extended Display Identification Data)/DDC (Display Data Channel) . ■ Summary ● It is established in VESA, for communication between PC and Monitor without order from for building condition. It helps to make easily use realize “Plug and Play” function. ● For EDID data write, we use DDC2B protocol. - Auto ■ After enter Service Mode by pushing “ADJ” key, ■ Enter EDID D/L mode. ■ Enter “START” by pushing “OK” key. * Caution: - N ever connect HDMI & D-sub Cable when the ing . - Use the proper cables below for EDID Writing

LGE Internal Use Only

■ It only needs to PCM EDID D/L for North America Product.

■ EDID data (Model name = LG TV) - RGB HD 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 01 16 01 03 68 A0 5A 78 0A EE 91 A3 54 4C 99 26 0F 50 54 A1 08 00 31 40 45 40 61 40 01 01 01 01 01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88 36 00 B0 84 43 00 00 18 A0 0F 20 00 31 58 1C 20 28 80 14 00 B0 84 43 00 00 1E 00 00 00 FD 00 3A 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 00 58 - North America _2D_HD_PCM ONLY HDMI 1 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26

* Edid data and Model option (RS232) NO

Enter MODE

EDID data Model option

Item

‘Mode In’



CMD 1

A

A

CMD 2

A

E

Data 0

0

00

0

10

When transfer the ‘Mode In’, Carry the command.

Automatically (The use of a internal pattern)

0F 50 54 A1 08 00 31 40 45 40 61 40 01 01 01 01 01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88 36 00 B0 84 43 00 00 18 A0 0F 20 00 31 58 1C 20 28 80 14 00 B0 84 43 00 00 1E 00 00 00 FD 00 3A 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 3F 02 03 1D F1 48 10 84 05 02 03 20 22 01 23 09 57 07 67 03 0C 00 10 00 80 2D E3 05 03 01 01 1D 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 02

- Manual ■ Write HDMI EDID data ● Using instruments - Jig. (PC Serial to D-Sub connection) for PC, DDC adjustment. - S/W for DDC recording (EDID data write and read) - D-sub jack - Additional HDMI cable connection Jig. ● Preparing and setting. - Set instruments and Jig. Like pic.5), then turn on PC and Jig. - Operate DDC write S/W (EDID write & read) - It will operate in the DOS mode.

3A 80 18 71 38 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1D

< For write EDID data, setting Jig and another instruments >

Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes

-7-

LGE Internal Use Only

- North America _2D_HD_PCM ONLY HDMI 2

00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 3F

- Adjustment Color Temperature(White balance) ■ Using Instruments ● Color Analyzer: CA-210 (CH 10) - Using LCD color temperature, Color Analyzer (CA210) must use CH 10, which Matrix compensated (White, Red, Green, Blue compensation) with CS2100. See the Coordination bellowed one. ● Auto-adjustment Equipment (It needs when Auto-adjustment – It is availed communicate with RS-232C : Baud rate: 115200) ●V ideo Signal Generator MSPG-925F 720p, 216Gray (Model: 217, Pattern 78)

02 03 1D F1 48 10 84 05 02 03 20 22 01 23 09 57

■ Connection Diagram (Auto Adjustment) ● Using Inner Pattern

00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 0F 50 54 A1 08 00 31 40 45 40 61 40 01 01 01 01 01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88 36 00 B0 84 43 00 00 18 A0 0F 20 00 31 58 1C 20 28 80 14 00 B0 84 43 00 00 1E 00 00 00 FD 00 3A 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC

07 67 03 0C 00 20 00 80 2D E3 05 03 01 01 1D 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0D ● Using HDMI input

- North America _2D_HD_PCM ONLY HDMI 3 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 0F 50 54 A1 08 00 31 40 45 40 61 40 01 01 01 01 01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88 36 00 B0 84 43 00 00 18 A0 0F 20 00 31 58 1C 20 28 80 14 00 B0 84 43 00 00 1E 00 00 00 FD 00 3A 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC

< connection Diagram for Adjustment White balance >

00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 3F

■ White Balance Adjustment If you can’t adjust with inner pattern, then you can adjust it using HDMI pattern. You can select option at “Ez-Adjust Menu – 7. White Balance” there items “NONE, INNER, HDMI”. It is normally setting at inner basically. If you can’t adjust using inner pattern you can select HDMI item, and you can adjust.

02 03 1D F1 48 10 84 05 02 03 20 22 01 23 09 57 07 67 03 0C 00 30 00 80 2D E3 05 03 01 01 1D 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 71 1C 16 20 58 2C 25 00 40 84 63

In manual Adjust case, if you press ADJ button of service remocon, and enter “Ez-Adjust Menu – 7. White Balance”, then automatically inner pattern operates. (In case of “Inner” originally “Test-Pattern. On” will be selected in The “Test-Pattern. On/Off”.

00 00 9E 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 FD

- See Working Guide if you want more information about EDID communication.

Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes

-8-

● Connect all cables and equipments like Pic.5) ●S et Baud Rate of RS-232C to 115200. It may set 115200 orignally. ● Connect RS-232C cable to set ● Connect HDMI cable to set

LGE Internal Use Only

● When Color temperature (White balance) Adjustment (Automatically) - Press “Power only key” of service remocon and operate automatically adjustment. - Set BaudRate to 115200. ● You must start “wb 00 00” and finish it “wb 00 ff”. ● If it needs, then adjustment “Offset”. ■ White Balance Adjustment (Manual adjustment) ● Test Equipment: CA-210 - Using PDP color temperature, Color Analyzer (CA-210) must use CH 10, which Matrix compensated (White, Red, Green, Blue compensation) with CS-2100. See the Coordination bellowed one. ● Manual adjustment sequence is like bellowed one. - Turn to “Ez-Adjust” mode with press ADJ button of service remocon. - Select “10.Test Pattern” with CH+/- button and press enter. Then set will go on Heat-run mode. Over 30 minutes set let on Heat-run mode. - Let CA-210 to zero calibration and must has gap more 10cm from center of PDP module when adjustment. - Press “ADJ” button of service remocon and select “7.White-Balance” in “Ez-Adjust” then press “►” button of navigation key. (When press “►” button then set will go to full white mode) - Adjust at three mode (Cool, Medium, Warm) - If “cool” mode Let B-Gain to 192 and R, G, B-Cut to 64 and then control R, G gain adjustment High Light adjustment. - If “Medium” and “Warm” mode Let R-Gain to 192 and R, G, B-Cut to 64 and then control G, B gain adjustment High Light adjustment. - All of the three mode Let R-Gain to 192 and R, G, B-Cut to 64 and then control G, B gain adjustment High Light adjustment. - With volume button (+/-) you can adjust. - After all adjustment finished, with Enter (■ key) turn to Ez-Adjust mode. Then with ADJ button, exit from adjustment mode

■ RS-232C Command (Commonly apply) RS-232C COMMAND [CMD ID DATA]

Meaning

wb

00

00

White Balance adjustment start.

wb

00

10

Start of adjust gain

wb

00

1f

End of gain adjust

wb

00

20

Start of offset adjust

(Inner white pattern)

(Inner white pattern) wb

00

2f

End of offset adjust

wb

00

ff

End of White Balance adjust (Inner pattern disappeared)

● “wb 00 00”: Start Auto-adjustment of white balance. ● “wb 00 10”: Start Gain Adjustment (Inner pattern) ● “jb 00 c0” : ●… ● “wb 00 1f”: End of Adjustment * If it needs, offset adjustment (wb 00 20-start, wb 00 2fend) ● “wb 00 ff”: End of white balance adjustment (inner pattern disappear)

* Attachment: W hite Balance adjustment coordination and color temperature. ● Using CS-1000 Equipment. - COOL : T=11000K, ∆uv=0.000, x=0.276 y=0.283 - MEDIUM : T=9300K, ∆uv=0.000, x=0.285 y=0.293 - WARM : T=6500K, ∆uv=0.000, x=0.313 y=0.329

■ Adjustment Mapping information RS-232C COMMAND [CMD ID DATA] Cool

Mid

Warm

M I N

CENTER (DEFAULT) Cool

Mid

Warm

M A X

R Gain

jg

Ja

jd

00

184

192

192

192

G Gain

jh

Jb

je

00

187

183

159

192

B Gain

ji

Jc

jf

00

192

161

95

192

64

64

64

127

R Cut G Cut

64

64

64

127

B Cut

64

64

64

127

Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes

-9-

LGE Internal Use Only

6. GND and ESD Testing

6.1. Prepare GND and ESD Testing.

● When tester will measure on Cool condition, adjust W30 on TV display menu.

■ Check the connection between set and power cord

6.2. Operate GND and ESD auto-test.

■ Fully connected (Between set and power cord) set enter the Auto-test sequence. ■ Connect D-Jack AV jack test equipment. ■ Turn on Auto-controller(GWS103-4) ■ Start Auto GND test. ■ If its result is NG, then notice with buzzer. ■ If its result is OK, then automatically it turns to ESD Test. ■ Operate ESD test ■ If its result is NG, then notice with buzzer. ■ If its result is OK, then process next steps. Notice it with Good lamp and STOPER Down.

● When tester will measure on medium condition, adjust 0 on TV display menu.

● When tester will measure on warm condition, adjust W30 on TV display menu. ● Using CA-210 Equipment. (10 CH) - Contrast value: 216 Gray Color temperature

Test Equipment

6.3. Check Items.

Color Coordination x

■ Test Voltage ● GND: 1.5KV/min at 100mA ● Signal: 3KV/min at 100mA ■ Test time: just 1 second. ■ Test point ● GND test: Test between Power cord GND and Signal cable metal GND. ● ESD test: Test between Power cord GND and Live and neutral. ■ Leakage current: Set to 0.5mA(rms)

y

COOL

CA-210

0.276 ± 0.002

0.283 ± 0.002

MEDIUM

CA-210

0.285 ± 0.002

0.293 ± 0.002

WARM

CA-210

0.313 ± 0.002

0.329 ± 0.002

- Brightness spec. Item

White average brightness

Min

49

Typ

60

Max Unit Remark

Brightness uniformity -20

6.4. POWER PCB Ass’y Voltage adjustment (Va, Vs voltage adjustment)

+20 cd/m²

%

- 100% Window White Pattern - 100IRE(255Gray) - Picture: Vivid(Medium)

- 85IRE(216Gray) 100% Window White Pattern - Picture: Vivid(Medium)

6.4.1. Test equipment : D.M.M 1EA 6.4.2. Connection Diagram for Measuring : refer to fig.1 <XPOWER4 42T4 PSU>

5.3. Test of RS-232C control.

- Press In-Start button of Service Remocon then set the “4.Baud Rate” to 115200. Then check RS-232C control and

5.4. Selection of Country option.

- Selection of country option is allowed only North American model (Not allowed Korean model). It is selection of Country about Rating and Time Zone. ■ Models: All models which PU11A Chassis (See the first page.) ■ Press “In-Start” button of Service Remocon, then enter the “Option” Menu with “PIP CH-“ Button ■ Select one of these three (USA, CANADA, MEXICO) depends on its market using “Vol. +/-“button. * Caution : Don’t push The INSTOP KEY after completing the function inspection. * Caution : Inspection only PAL M / NTSC

Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes

(fig.1) PCB Assy Voltage adjustment

6.4.3. Adjustment method

6.4.3.1. Vs adjustment (refer fig.1) (1) Connect + terminal of D.M.M. to Vs pin of P811, connect -terminal to GND pin of P811 (2) After turning VR901, voltage of D.M.M adjustment as same as Vs voltage which on label of left/top ( deviation ; ±0.5V) 6.4.3.2. Va adjustment (refer fig.1) (1) After receiving 100% Full White Pattern, HEAT RUN. (2) Connect + terminal of D.M.M. to Va pin of P811, connect -terminal to GND pin of P811 (3) After turning VR502,voltage of D.M.M adjustment as same as Va voltage which on label of left/top (deviation; ±0.5V)

- 10 -

LGE Internal Use Only

7. Default Service option.

■ Select file (epk file)

7.1. ADC-Set.

■ R-Gain adjustment Value (default 128) ■ G-Gain adjustment Value (default 128) ■ B-Gain adjustment Value (default 128) ■ R-Offset adjustment Value (default 128) ■ G-Offset adjustment Value (default 128) ■ B-Offset adjustment Value (default 128)

7.2. White balance. Value. Center(Default) COOL

Mid

Warm

R Gain

192

192

192

G Gain

192

192

192

B Gain

192

192

192

R Cut

64

64

64

G Cut

64

64

64

B Cut

64

64

64

7.3. Temperature Threshold ■ Threshold Down Low ■ Threshold Up Low ■ Threshold Down High ■ Threshold Up High

20 23 70 75

8. USB (*.epk file ) ■ Put the USB Stick to the USB socket ■ Press Menu key, and move OPTION

■ After is finished, remove the USB stick. ■ Press “IN-START” key of ADJ remote control, check the S/W version.

9. Tool option ■ Press “FAV” Press 7 times

Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes

- 11 -

42PA4500-UM

42PA450C-UM

Tool option 1

24576

24576

Tool option 2

22794

22794

Tool option 3

3697

3697

Tool option 4

55247

55247

Tool option 5

10

10

Country code

02

02

Country Group

US

US

Country

US

US

LGE Internal Use Only

BLOCK DIAGRAM

Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes

- 12 -

LGE Internal Use Only

EXPLODED VIEW IMPORTANT SAFETY NOTICE

A12 A9

201 302

501

A2

910

400

900

120

240

590

LV1

202

205

203

200

A10

204

520

601

304

580

301

206

305

207

303

540

300

310

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and EXPLODED VIEW. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.

Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes

- 13 -

LGE Internal Use Only

+5V

Full SCART

E

E DUP_DVB ISA1530AC1 Q103-*1

+3.3V

EU JK100 PSC008-02

PDP GP4 S7LR3 EAX64696601

L103-*1 CB1608UA121T

L103 120-ohm EU

B

DUP_DVB

C

C

R104 10K EU

E DUP_DVB 2SC3052 Q100-*1

AV/SC1_DET R105 1K EU

SHIELD

DUP_DVB 2SC3052 Q104*-1

B

B

R129 0 EU

B SC1_SOG_IN

C C

23 B

AV/SC1_CVBS_IN

AV_DET COM_GND

C111 220pF 50V EU

C109 27pF 50V EU

R117 75 EU

22 21 SYNC_IN 20

C106

SYNC_OUT 19 SYNC_GND1

EU

5% 1/16W

R113 75 EU

SYNC_GND2 18

R118 470K EU

R144 470 EU

E

C

Q100 MMBT3904(NXP) EU

Q103 MMBT3906(NXP) EU

R136 330 EU

E

R146 18K EU C B

E Q104 MMBT3904(NXP) EU

SC1_VOUT

0

17

R141 220 EU

R135 0 EU

R134 100 1/4W EU

C116 10uF 16V EU

R147 10K EU

R143 180 EU

DTV/MNT_VOUT E DUP_DVB 2SC3052 Q106-*1

E DUP_DVB 2SC3052 Q105-*1

B C

RGB_IO

B C

SC1_FB

16 R_OUT

R119 75 EU

SC1_R+/COMP1_Pr+

15 RGB_GND

R106 75

14 R_GND

R114 10K EU

D2B_OUT 12 G_OUT

REC_8

10

R121 10K EU

R115 470K EU

G_GND 9 ID

R126 12K EU

AUDIO_L_IN 6

R107 75

EU R155 3K B

AV/SC1_R_IN R124 10K EU

SC_RE2

EU 7.5K R156

E

A1 DUP_DVB 2SC3052 Q107-*1

R116 470K EU

B_GND

EU 1K R157

C

SC1_B+/COMP1_Pb+

7

E

EU 12K R159

C

8 B_OUT

SC_RE1

B

EU MMBT3904(NXP) B Q105 C

EU MMBT3904(NXP) B Q107

DUP_DVB D112-*1 KDS184 A2

AV/SC1_L_IN

EU C 12K R160

E

A1

R108 75

D2B_IN

C

R120 2.7K EU

SC1_G+/COMP1_Y+

11

EU MMBT3904(NXP) Q106

EU MMBD6100 D112 A2 SC1_ID

13

EU 1K R158

E

R123 33 EU

P_17V IC101 AZ4580MTR-E1 P_17V

C

R127 12K EU

5 AUDIO_GND 4 AUDIO_L_OUT C107 5600pF 50V EU C108 5600pF 50V EU

3 AUDIO_R_IN 2 AUDIO_R_OUT 1

R138 2K EU Q101 MMBT3904(NXP) EU

C114 27pF 50V EU

C113 10uF 16V EU

R149 15K EU

R145 6.8K EU

R137 2K EU

1

8

VCC

IN1-

2

7

OUT2

IN1+

3

6

IN2-

VEE

4

5

IN2+

SCART1_Lout R154 5.6K EU

E DUP_DVB 2SC3052 Q101-*1

OUT1

EU 5.6K R153

SCART1_Rout

B C115 27pF 50V EU

C

DTV_R_OUT R139 2K EU Q102 MMBT3904(NXP) EU

C112 10uF 16V EU

+3.3V_ST

R152 6.8K EU

R148 15K EU

EU R189 10K SCART1_MUTE

R140 2K EU

E DUP_DVB 2SC3052 Q102-*1

B C

EU

/PCM_OE /PCM_WE

CI_WE CI_IORD

/PCM_IORD

CI_IOWR

/PCM_IOWR AR106

C101 0.1uF 16V EU

EU

33

CI_ADDR[12]

PCM_A[12]

CI_ADDR[13]

PCM_A[13]

CI_ADDR[14]

PCM_A[14] /PCM_REG

REG

BUF2_FE_TS_DATA[0-7] BUF2_FE_TS_DATA[0]

+5V

EU

PCM_D[3] PCM_D[4]

4

PCM_D[5]

5

PCM_D[6]

CI_TS_DATA[6] CI_TS_DATA[7]

40

6

41

7

PCM_D[7] R130 33 EU 1/16W R1315% 33 EU

37 33

R111 10K EU

BUF2_FE_TS_DATA[0] BUF2_FE_TS_DATA[1] BUF2_FE_TS_DATA[2]

READY R112 0

BUF2_FE_TS_DATA[3]

9

CI_ADDR[10]

44

10

CI_ADDR[11]

11

CI_ADDR[9]

46

12

CI_ADDR[8]

47

13

CI_ADDR[13]

48

14

CI_ADDR[14]

49

15

50

16

BUF2_FE_TS_DATA[4] BUF2_FE_TS_DATA[5]

R109 10K EU

BUF2_FE_TS_DATA[6] BUF2_FE_TS_DATA[7] R100 EU 33 R101 EU 33

17 18

53

19

54

20

55

R132

100 EU

READY

BUF2_FE_TS_VAL_ERR BUF2_FE_TS_CLK

21

CI_ADDR[12]

56

22

57

23

CI_ADDR[7] CI_ADDR[6]

26

CI_ADDR[3]

61

27

CI_TS_VAL

62

28

CI_TS_SYNC

63

29

64

30

65

31

PCM_D[1]

66

32

PCM_D[2]

67

33

33 EU

CI_TS_DATA[1] CI_TS_DATA[2]

68

AR109 33 EU BUF2_FE_TS_DATA[4] BUF1_FE_TS_DATA[4] BUF2_FE_TS_DATA[5]

BUF1_FE_TS_DATA[5]

BUF2_FE_TS_DATA[6]

BUF1_FE_TS_DATA[6]

BUF2_FE_TS_DATA[7]

BUF1_FE_TS_DATA[7]

1A2

PCM_A[1] 2Y3

CI_ADDR[6]

1A4

PCM_A[3] 2Y1

CI_ADDR[4] GND

1

2

EU

20

19

3

18

4

17

5

16

6

15

7

14

8

13

9

12

10

11

EU C105 0.1uF 16V

AR110 33 BUF1_FE_TS_SYN

VCC

BUF1_FE_TS_VAL_ERR

2OE

BUF1_FE_TS_CLK

EU

BUF2_FE_TS_SYN BUF2_FE_TS_VAL_ERR BUF2_FE_TS_CLK

1Y1

CI_ADDR[0] 2A4

PCM_A[7] 1Y2

CI_ADDR[1] 2A3

PCM_A[6] 1Y3

CI_ADDR[2] 2A2

PCM_A[5] 1Y4

CI_ADDR[3] 2A1

PCM_A[4]

L100-*1 CB1608UA121T

CI POWER ENABLE CONTROL +5V

DUP_DVB Q114 ZXMP3F30FHTA L100 EU 120-ohm EU

CI_ADDR[2] R184 10K READY

CI_ADDR[1] EU

AR104 33

CI_ADDR[0]

R187 10K EU

+5V

+5V_CI_ON

C104 0.1uF 16V EU

R198 10K READY

PCM_D[0]

3.3V_CI

AO3407A

+3.3V

CI_ADDR[0-14]

L101-*1 CB1608UA121T +3.3V_CI DUP_DVB

G

34

CI_TS_DATA[3] R150 10K EU

C131 0.1uF 16V READY

G

S

R110 0 READY AR102

2Y4

2Y2

60

CI_TS_DATA[0]

1A1

1A3

CI_ADDR[4]

33 EU

1OE

CI_DET PCM_A[0]

PCM_A[2]

CI_ADDR[5]

AR101

IC100 TC74LCX244FT

CI_ADDR[5]

25

REG

EU R165 10K

CI_OE

/PCM_IRQA

24

/PCM_WAIT

+3.3V_CI

0

58

CI_TS_CLK

PCM_A[11]

+3.3V_CI

CI_WE

59

PCM_RST

PCM_A[10]

CI_ADDR[7]

R128

BUF1_FE_TS_DATA[3]

CI_ADDR[10]

BUF1_FE_TS_DATA[0-7]

8

51

BUF1_FE_TS_DATA[1] BUF1_FE_TS_DATA[2]

BUF2_FE_TS_DATA[3]

/PCM_CE

42

52

BUF2_FE_TS_DATA[2]

PCM_A[9]

CI_ADDR[11]

R133 10K EU

43 45

CI_IOWR

PCM_A[8]

D

3

39

EU

BUF2_FE_TS_SYN BUF2_FE_TS_DATA[0-7]

AR103 33

38

AR100

CI_IORD

BUF2_FE_TS_DATA[0-7]

EU

36

CI_TS_DATA[5]

CI_TS_DATA[4]

33

D

R102 100 EU

AR107

CI_ADDR[8] CI_ADDR[9]

S

/CI_CD1

JK102 10067972-000LF EU 35

AR108 33 EU BUF1_FE_TS_DATA[0]

5% 1/16W

R151 10K EU

BUF2_FE_TS_DATA[1]

BUF1_FE_TS_DATA[0-7]

+5V_CI_ON

C100 22uF 10V EU

33

AR105

CI_OE

CI SLOT

2 G2

69

R103 100 EU

/CI_CD2

G1 1

MULTI Q114-*1

C PCM_D[0-7]

PCM_5V_CTL PCM_D[0-7]

B R181 10K EU

L101 120-ohm EU

Q113 MMBT3904(NXP) EU E

C136 0.1uF 16V READY

E DUP_DVB 2SC3052 Q113*-1

C137 0.1uF 16V EU

B C

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

GP4_S7LR3 SCART,CI Slot

2011-12-01 1

7

LGE Internal Use Only

SPDIF

DATA1DATA0+

DATA0_SHIELD DATA0CLK+ CLK_SHIELD CLKCEC NC SCL

DDC_SDA_1

SDA

+5V_POWER

JP202

R208 33 HDMI_1

14 13

9 8 7 6

4 3 2

5

19

6

R227 1.8K SIDE_HDMI_1

7 8

18

9 10 11

R286 10K SIDE_HDMI_1

17

12 13 14 15

Q201 MMBT3904(NXP) SIDE_HDMI_1 E R230 3.3K R231 R287 SIDE_HDMI_1 33 10K SIDE_HDMI_1 SIDE_HDMI_1

R237 10K SIDE_HDMI_1

Q202 R241 1.8K SIDE_HDMI_2MMBT3904(NXP) SIDE_HDMI_2

19

R250 10K SIDE_HDMI_2 E R244 3.3K R289 SIDE_HDMI_2 R245 10K 33 SIDE_HDMI_2 SIDE_HDMI_2 DDC_SDA_3

R288 10K SIDE_HDMI_2

17

R209 10K SIDE_HDMI_2 HPD3

16

1 2

C B

18

DDC_SDA_2

16

16

20

VCC C219 0.1uF 16V

VINPUT

R285 100 SPDIF_OUT

GND

2

VCC

3

VIN

4

C220 10pF 50V

FIX_POLE

1

17

DDC_SCL_2

18

15

19 20 SHIELD

14 13

CEC_REMOTE

R232 33 SIDE_HDMI_1

CEC_REMOTE CK-_HDMI2

12 11 10 9

D0-_HDMI1

8

D0_GND

7

D0+ D0+_HDMI1

6

D1D1-_HDMI1 D1_GND

5

D1+

4 D1+_HDMI1 3

D2D2-_HDMI1

2

D2_GND

1

D2+

15

R246 33 SIDE_HDMI_2

14 13

CK+_HDMI2 D0-_HDMI2

9

D0D0_GND

8

D0+ D0+_HDMI2

7

D1-_HDMI2

6

D1D1_GND

5

D1+ D1+_HDMI2 D2D2-_HDMI2 D2_GND

4 3 2

D2+ D2+_HDMI2

D2+_HDMI1

CEC_REMOTE

1

R268 100

CEC_REMOTE

CEC_REMOTE_S7

CK-_HDMI3

12 11 10

CK+

DDC_SCL_3

SIDE USB

CK+

PEN_TOUCH +5V_ST D225 B140A

1A SPEC IC207

+3.3V 2

+5V

IC204 AP2191SG-13

GND

D0-_HDMI3

R264 10K

D0_GND D0+

NC

OUT_2

D0+_HDMI3

JK209 3AU04S-305-ZC-(LG)

D1D1-_HDMI3 D1_GND D1+ D1+_HDMI3 D2D2-_HDMI3 D2_GND D2+ D2+_HDMI3

+3.3V

VOUT

1

40V

D0-

SWITCH ADDED

AP2337SA-7

PEN_TOUCH VIN 3

CK+_HDMI3

8

1

7

2

GND

R270 10K

IN_1

$0.11 OUT_1

R258 33

C213 10uF 10V

C212 0.1uF 16V

FLG

6

3

5

4

IN_2

EN

USB1_CTL

R271 33

USB1_OCD SIDE_USB_DM

SIDE_USB_DP

JK201 SIDE_HDMI_1

JK200 HDMI_1

JK202 SIDE_HDMI_2

JK211 PPJ239-01 NON_EU 6H

5

4

1

R203 10K SIDE_HDMI_1 HPD2

B

CK+_HDMI1

D0-

C

4

USB DOWN STREAM

5

CK+

R226 1K SIDE_HDMI_1

3

CK-_HDMI1

12 11 10

HPD

DDC_SCL_1

20

2

+5V

SHIELD

DATA1_SHIELD

HPD1

DDC/CEC_GND

15

For CEC

1

DATA1+

5V_DET_HDMI_3 R240 1K SIDE_HDMI_2

2

16

DATA2-

BODY_SHIELD

JK204-*1 DUP_DVB 2F01TC1-CLM97-4F

DUP_AT

GND

3

R217 10K HDMI_1

DATA2_SHIELD

JP205

R281 10K HDMI_1

17

Q200 MMBT3904(NXP) HDMI_1 E R204 3.3K R207 R282 HDMI_133 10K HDMI_1 HDMI_1 JP201

R201 1.8K HDMI_1

18

B C

5V_DET_HDMI_2

3

HDMI1_NON Screw DATA2+ 1

R202 10K HDMI_1

C B

19

JK204 JST1223-001 B

4

YKF45-7058V

JP204

5V_DET_HDMI_1

R200 1K HDMI_1

+5V

C BODY_SHIELD

JK200-*1

SHIELD

E DUP_DVB 2SC3052 Q202-*1

Fiber Optic

DUP_DVB 2SC3052 Q201-*1

+5V B C

20

SIDE_HDMI_2

JP207

+5V

E

Fiber Optic

SIDE_HDMI_1

E DUP_DVB 2SC3052 Q200-*1

JP208

HDMI_1

10mm

COMPONENT2

ETHERNET

RS232C

[RD1]E-LUG

+2.5V

5H

[RD1]O-SPRING_2

4H

[RD1]_2

JK210 XRJV-01V-0-D12-080

JK208 PPJ234-02 EU

[GN]E-LUG

+3.3V

R251 75

6A [GN]O-SPRING

COMP2_Y+

5A

1

2

R259 10K

R266 1K

[GN]

5G

[WH1]O-SPRING

[BL]E-LUG-S

R252 75

3

4

COMP2_DET

ET_NET 5

COMP2_Pb+

[RD1]_1

5B

[RD]O-SPRING_1

[RD1]O-SPRING_1

6

R253 75

7C

+3.3V_ST COMP2_Pr+

5E

[WH]O-SPRING

4E

[RD]_2

5E

7E

[BL1]E-LUG-S

4D

[GN1]

COMP2_L_IN

R256 10K 5D

6E

R262 12K

R254 470K

JK203 SPG09-DB-009

R278 10K

R276 100 R263 12K

+5V_ST

7

GND

R277 100

[RD]E-LUG

DOUT1

3 R228 10K USA

RIN1 TX

C Q204 MMBT3904(NXP) USA

5

[GN1]O-SPRING

10

R229 100K USA B

ROUT1

R233 100K USA

DIN1

DIN2

[GN1]E-LUG ROUT2

[RD2]E-LUG

DUP_AT 2SC3052 Q204*-1 NON_EU R234 10K

[RD2]

5M

[WH2]O-SPRING

R235 470K

R236 12K

4

RP

5

5

6

8

2

3

4

5

6

7

6

RN C200 0.1uF 16V ET_NET

7

8

8

9

D204 D200 5.6V 5.6V ET_NET ET_NET

D205 5.6V ET_NET

D206 5.6V ET_NET

9

8

C1+

15

2

14

3

13

4

12

5

11

6

10

7

9

8

V+

C1-

C228 0.1uF 16V C225 0.1uF 16V

R273 0 ET_NET

R291 0 ET_NET

R280 0 ET_NET

R290 0 ET_NET

C2+

C2-

C226 0.1uF 16V

V-

DOUT2

RIN2

C227 0.1uF 16V B

C AV/SC1_R_IN NON_EU

[RD2]O-SPRING_2

4N

1

E

NON_EU

5N

16

4

E

6N

4

9

VCC

9

6D

3

TN

1 ET_NET_UDE

9

6

8

5D

7

C229 0.1uF 16V

PM_RXD

IC206 MAX3232CDR

2

R255 470K

+3.3V_ST

22

R279 10K

1 COMP2_R_IN

R257 10K

[RD]O-SPRING_2

PM_TXD

22

R284

[RD]_1 4C

[BL1]O-SPRING

R283

JP241

5C

7F

1

3

7

R267 1K

[RD]E-LUG-S

[RD1]E-LUG-S

BS-R430051

2

AV2_DET

R265 10K

[BL]O-SPRING

5F

TP 2

4A 7B

4F

JK210-*1

1

NON_EU

R242 12K

AV/SC1_L_IN

RGB PC

PC AUDIO

JK205 SPG09-DB-010

+5V_ST

[RD2]O-SPRING_1

7L

[RD2]E-LUG-S

JK206 PEJ027-04

R298 10K

R297 10K

SC1_R+/COMP1_Pr+

3

GND_2

1

11

R214 75

RED

7

[BL2]O-SPRING

DDC_DATA

2

12

SC1_B+/COMP1_Pb+

BLUE_GND

8

7K

[BL2]E-LUG-S +3.3V

4J

[GN2]

5J

[GN2]O-SPRING

H_SYNC

3 NON_EU R248 10K

13

V_SYNC

14

15

RGB_DDC_SDA

R216 75

DSUB_HSYNC

DSUB_G+

+3.3V

B_TERMINAL1

C203 10pF 50V

DSUB_VSYNC R224 10K

R225 1K

R220 10K PC_R_IN

4

R_SPRING

5

T_SPRING

DSUB_B+

R206 33 C202 10pF 50V

T_TERMINAL1

7A

R218 470K

WIRED IR

R222 12K JK207 PEJ027-04 USA

7B

B_TERMINAL2

6B

T_TERMINAL2

PC_L_IN R223 12K

16

R211 10

E_SPRING

6A

T_TERMINAL1

7A

B_TERMINAL1

IR

DSUB_DET RGB_DDC_SCL PC_SER_DATA

DDC_GND

3

R221 10K R219 470K

R212 10

SC1_G+/COMP1_Y+

[GN2]E-LUG

R215 75

DDC_CLOCK

5

6J

GND_1 SYNC_GND

10

COMP1_DET

R205 33

BLUE NC

9 4

NON_EU R249 1K

GREEN

6A DSUB_R+

GREEN_GND

5K

E_SPRING

RED_GND

6

1/16W 5%

5L

NON_EU

NON_EU R239 10K R238 470K

4

R_SPRING

5

T_SPRING

R213 0 NON_USA

PC_SER_CLK 7B

B_TERMINAL2

6B

T_TERMINAL2

SHILED

TX R210 10 USA

GND

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

GP4_S7LR1 JACK INTERFACE

2011-12-1 2

7

LGE Internal Use Only

TUNER

BUF1_FE_TS_DATA[0-7] FE_TS_DATA[0]

BUF1_FE_TS_DATA[0]

R323

FNIM R324 FNIM R326 0 FNIM R325 FNIM 0

FE_TS_DATA[1] FE_TS_DATA[2]

BUF1_FE_TS_DATA[1]

0

FE_TS_DATA[3]

BUF1_FE_TS_DATA[2] BUF1_FE_TS_DATA[3]

0 G201D_NON_DEMODE TU302-*1 TDSS-G201D

FNIM R328 FNIM R330 FNIM 0 R329 0 FNIM

FE_TS_DATA[5]

TUNER

OPT1

TDSS-G201D

DVB-T/C

OPT2 HNIM

OPT3 X

1 2 3 4

TDSS-H201F

ATSC

X

HNIM

5 6

TDSH-T101F

DVB-T_SCA HNIM

RF_SW

7 8

TDSN_B001F TDSN_G301D

SBTVD DVB_T2

FNIM

9

RF_SW

10 11

FNIM

X

BUF1_FE_TS_DATA[5]

0

FE_TS_DATA[6] FE_TS_DATA[7]

NC_1

BUF1_FE_TS_DATA[4]

R327

FE_TS_DATA[4]

RESET

BUF1_FE_TS_DATA[6] BUF1_FE_TS_DATA[7]

0

SCL

FE_TS_DATA[0-7] R331

SDA

FE_TS_SYN

+B1[3.3V]

0

FE_TS_VAL_ERR

0

FE_TS_CLK

NC_2

R333 R332

FNIM

BUF1_FE_TS_SYN

FNIM

BUF1_FE_TS_VAL_ERR

FNIM

BUF1_FE_TS_CLK

0 +B2[1.8V] NC_3 IF_AGC DIF[P] DIF[N]

RF_SWITCH 12

R310 1K SHIELD

RF_SWITCH_CTL C307 0.1uF 16V RF_SWITCH

Close to Tuner Pin TU303 TDSN_B001F

TU304 TDSN-G301D 1 2 3 4 5 6 7 8 9 10 11

+1.25V_TU

12 13 C300 10uF 6.3V FNIM

C301 0.1uF 16V FNIM

14 15 16 17 18 19 20 21 22 23 24 25 26 27

NC_1

1

RESET

2

SCL

3

SDA

4

+B1[3.3V]

5

SIF

6

+B2[1.8V]

7

CVBS

8

NC_2

9

NC_3

10

NC_4

11

+B3[3.3V]

12

+B4[1.23V]

13

NC_5

14

GND

15

ERROR

16

SYNC

17

VALID

18

MCLK

19

D0

20

D1

21

D2

22

D3

23

D4

24

D5

25

D6

26

D7

ATSC

DVB_T/C

SBTVD

DVB_T2

27

RF_S/W_CTL

1

RESET

2

SCL

3

SDA

4

+B1[3.3V]

5

SIF

6

+B2[1.8V]

7

CVBS

8

NC_1

9

NC_2

10

NC_3

11

NC

2

SCL

3

SDA

4

+3.3V

5

SIF

6

+1.8V

7

CVBS

8

IF_AGC

9

DIF[P]

10

DIF[N]

11

NC_1

1

RESET

2

SCL

3

SDA

4

+B1[3.3V]

5

NC_2

6

+B2[1.8V]

7

NC_3

8

IF_AGC

9

DIF[P]

10

DIF[N]

11

NC_4

12

12

12 SHIELD

SHIELD

RF_S/W_CTL RESET

R308 R301 2.2K 100

SCL

R307

R311 10K TUNER_RESET

+B1[3.3V] SIF +B2[1.8V] CVBS IF_AGC

TU_SCL

22

R306 22

SDA

C302 0.1uF 16V

C303 10uF 16V

DVB_T2 0 H_NIM 0

16V 0.1uF C310

C304 68pF 50V

TU_SDA

C305 68pF 50V

C311 0.1uF 16V

Close to Tuner Pin

R302 R303 IF_AGC_MAIN

DIF[P]

IF_P_MSTAR DIF[N]

IF_N_MSTAR

SHIELD

R320

Close to Tuner Pin NON_A_DEMODE 430

GND

R309 2.2K

DVB_T2 16V 0.1uF C306

+B3[3.3V] +B4[1.23V]

2K

NON_A_DEMODE

R319

ERROR

+5V NON_A_DEMODE 430 R322

SYNC

C308 0.1uF 16V

FE_TS_SYN VALID FE_TS_VAL_ERR MCLK D0

FE_TS_CLK FE_TS_DATA[0]

D1

FE_TS_DATA[1]

+2.5V_TU

+1.8V_TU

DVB_T_SCA 1

RESET

+3.3V_TU

+3.3V_TU

TU300 TDSH-T101F

TU301 TDSS-H201F

TU302 TDSS-G101D

FE_TS_DATA[0-7]

C312 10pF 50V READY

A_DEMODE R317 82

R316 470 A_DEMODE

R312 4.7K A_DEMODE A_DEMODE

TU_SIF

E

B C

MMBT3906(NXP) Q301 A_DEMODE

R334

D2

FE_TS_DATA[2]

D3

FE_TS_DATA[3]

D4

FE_TS_DATA[4]

D5

FE_TS_DATA[5]

D6

FE_TS_DATA[6]

D7

FE_TS_DATA[7]

C313 10pF 50V READY

0 A_DEMODE

TU_CVBS

Close to Tuner Pin

28

28 SHIELD

SHIELD

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

Tuner block

3

6

TUNER

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

LGE2111B

+3.3V

MODEL OPTION 1K

MODEL OPTION

R409

FHD

PIN NAME

MODEL_OPT_1

MODEL_OPT_0

AB3

MODEL_OPT_1

F4

MODEL_OPT_2

AB2

LOW

HIGH

FHD

HD

C468

100

DTV_IF

0.1uF

IF_P_MSTAR DVB_T_SCA C483 100pF

R443

C469

100

0.1uF

IF_N_MSTAR

H_NIM

H_NIM

DVB_T_SCA C486 100pF

HD

A_DEMODE A_DEMODE 47 C458 0.1uF R446 C459

0.1uF R447

TU_SIF

47

ANALOG SIF Close to MSTAR +3.3V

A_RXCN

J3

G5

NON_A_DEMODE

TUNER_I2C I2C_SCKM1/GPIO75

HOTPLUGA/GPIO19

I2C_SDAM1/GPIO76

AD6 CK+_HDMI3

AE6

CK-_HDMI3

AD7

D0+_HDMI3

AD8 AC7

D1-_HDMI3

AE8

D2-_HDMI3

AE5

DDC_SDA_3

AD5

HPD3

SPDIF_IN/GPIO152

C_RX1P

SPDIF_OUT/GPIO153 USB0_DM

C_RX2N

USB0_DP

A_DEMODE

USB1_DM

HOTPLUGC/GPIO21

USB1_DP

C461

F1

D0+_HDMI1

F2

D0-_HDMI1 D1+_HDMI1

F3 G3

D2+_HDMI1

G2

D2-_HDMI1

G7

DDC_SDA_1

AD4

X400 24MHz

C462

Close to MSTAR EU R456 10K

30pF

M7 P_SDA SPDIF_OUT

22

R474

I2S_OUT_BCK/GPIO156

D_RX1N

I2S_OUT_MCK/GPIO154

D_RX2P

I2S_OUT_SD/GPIO157

D_RX2N

I2S_OUT_WS/GPIO155

DSUB_R+

R412

22

R5

R413 R424

22 33

R4 C407

0.047uF

N1

R425

68

C408

0.047uF

N2

R426

DSUB_G+

R411 2.4K

33

C409

0.047uF

R427

68

C410

0.047uF

M3

R428

33

C411

0.047uF

L2

R429

68

C412

0.047uF

L3

C413

1000pF

M2

AUR1 AUL3

HSYNC0

AUR3

VSYNC0

AUL4

RIN0P

AUR4 AUOUTL2

GIN0M

AUOUTR2

BIN0P

SIDE_USB_DM

AD9

/CI_CD1

SIDE_USB_DP

SC1_G+/COMP1_Y+

C414

68

C415

0.047uF

T1

33

C416

0.047uF

R2

R435

68 33

R436

68

C417

R1

C418

0.047uF 0.047uF

C419

0.047uF

P2

C420 R430 R415

COMP2_Y+

NON_EU C421

0.047uF

68

C422

0.047uF

W2

C423

0.047uF

V1

C424 C425

0.047uF 0.047uF

V3

R419

68 33

R420

68

C426

0.047uF

U3

C427

1000pF

EARPHONE_OUTL

RIN1M

EARPHONE_OUTR

GIN1P RP

BIN1P

TP

BIN1M RN

TU_CVBS

EU R422 R423

AV/SC1_CVBS_IN COMP2_Y+

33 33

A_DEMODE C428 0.047uF EU C429 C430

C9

T4

0.047uF

T6

EU

/PCM_WAIT

PCM_A[13]

AA18

A8

Y3

C447

AA2

C448

2.2uF

AA1

C449

2.2uF

AA3

C450

2.2uF

W3

C451

2.2uF

Y2

C452

2.2uF

AC18

AE21 EU C495 0.1uF 16V

22

USB1_CTL

AB20

TS1SYNC/GPIO97

PCMADR8/GPIO108

TS1DATA0/GPIO88

PCMADR9/GPIO110

TS1DATA1/GPIO89

PCMADR10/GPIO114

TS1DATA2/GPIO90

PCMADR11/GPIO112

TS1DATA3/GPIO91

PCMADR12/GPIO104

TS1DATA4/GPIO92

PCMADR13/GPIO107

TS1DATA5/GPIO93

PCMADR14/GPIO106

TS1DATA6/GPIO94

PCMOE_N/GPIO113

NF_WPZ/GPIO198

PCMWE_N/GPIO197

NF_CEZ/GPIO137

PCMIORD_N/GPIO111

NF_CLE/GPIO136

PCMIOWR_N/GPIO109

NF_REZ/GPIO139

PCMCE_N/GPIO115

NF_ALE/GPIO141

PCMIRQA_N/GPIO105

NF_RBZ/GPIO142 GPIO_PM[0]/GPIO6

PCM_RESET/GPIO129

PM_UART_TX/GPIO_PM[1]/GPIO7

RGB_DDC_SCL

H5

R467

22

H4

PWM0 PWM1

BUF1_FE_TS_VAL_ERR

W13 Y14

BUF1_FE_TS_DATA[0]

AA14

BUF1_FE_TS_DATA[1]

AD13

BUF1_FE_TS_DATA[2]

Y13

BUF1_FE_TS_DATA[3]

AD12

BUF1_FE_TS_DATA[5]

AC12

BUF1_FE_TS_DATA[6] BUF1_FE_TS_DATA[7]

W10

AR401

22

OS

LED0/GPIO55

/PF_CE0

Y10

/PF_CE1

AB10

/PF_OE

AC9

/PF_WE

AD10

PF_ALE

AC10 AR400 R476

22

100

OS AC_DET

D4 L7

/F_RB

PM_TXD 100

R477

DISP_EN

1K PM_RXD

C4

UART1_TX/GPIO43

PM_SPI_SCZ2/GPIO_PM[10]/GPIO16

UART2_RX/GPIO64

GPIO_PM[11]/GPIO17

PM_SPI_CZ0/GPIO_PM[12]/GPIO0

I2C_SCKM2/DDCR_CK/GPIO72

PM_SPI_SDI/GPIO2

/FLASH_WP

B3

5V_ON

L4 A5

I2C_SDAM2/DDCR_DA/GPIO71

ERROR_DET

L6

R478

33

D3

R479

SPI_SCK

33

/SPI_CS

B5 B4

R480

SPI_SDI

33

SPI_SDO

PWM3/GPIO69

MAINU17 IC P17

PWM4/GPIO70

R17

PWM_PM/GPIO199

R18

PWM2/GPIO68

C7 LED_RED

T17

E7

L404-*1 CIS10P121AC

D7 J6 C1

AMP_MUTE

SAR0/GPIO31

T18

SAR1/GPIO32

U18

SAR2/GPIO33

J9

SAR3/GPIO34

J11

SAR4/GPIO35

P8 R8

DUP_AT

U11 V10

Boot from SPI CS1N(EXT_FLASH) Boot from SPI_CS0N(INT_FLASH)

TN

GIN2P

LED1/GPIO56

GIN2M

R440 49.9

B51_no_EJ SB51_WOS SB51_WS MIPS_SPE_NO_EJ MIPS_SPI_EJ_1 MIPS_SPI_EJ_2 MIPS_WOS MIPS_WS

K4 HWRESET

CVBS0 CVBS1

: : : : : : : :

4’b0000 4’b0001 4’b0010 4’b0100 4’b0101 4’b0110 4’b1001 4’b1010

J16 K16

L16 L17 LED_RED

GND_84

VDDC_5

GND_86

VDDC_6

GND_87

VDDC_7

GND_88

VDDC_8

GND_89

VDDC_9

GND_90

VDDC_10

GND_91

VDDC_11

GND_92

VDDC_12

GND_93 GND_94

AVDD25_PGA

PWM0

AVSS_PGA

AVDD_DDR0_C

GND_97

AVDD_DDR0_D_1

GND_98

AVDD_DDR0_D_2

GND_99

AVDD_DDR0_D_3

GND_100 GND_101

AVDD_DDR1_C

GND_102

AVDD_DDR1_D_1

GND_103

AVDD_DDR1_D_2

GND_104

AVDD_DDR1_D_3

GND_1 GND_2

AVDD25_PGA

GND_5

AVSS_PGA

GND_6 GND_7

Y8

AVDD_MOD 1uF

Close to MSTAR

Y4

DUP_DVB

L405 BLM18PG121SN1D

DDR3 1.5V

SOC_RESET

C4001 IS CAP FOR REPAIR SHOULD BE BOTTOM SIDE

AVDD2P5:172mA

+3.3V_ST

+1.5V_DDR

R408 10

AVDD_DDR1:55mA

DUP_AT 1uF

C446

0.1uF

C444

C445

0.1uF

C4004

0.1uF

0.1uF

C442

0.1uF C4003

10uF

C436

DUP_AT

DUP_DVB

Normal 2.5V AVDD_NODIE

R450 R451 3.3K 3.3K

R482 R483 3.3K 3.3K

MAIN N5 IC A6

5V_DET_HDMI_1 R452 2.2K

R453 2.2K

5V_DET_HDMI_2 I2C_SDA

M6

5V_DET_HDMI_3

R7

I2C_SCL

P5

P_SDA

D6

P_SCL

AVSS_PGA DUP_DVB Close to IC with width trace

Normal Power 3.3V

UART_RXD UART_TXD

CIS10P121AC DUP_AT

AMP_RESET_N

M4

TUNER_RESET

C8

PCM_5V_CTL CI_DET AMP_SCL

C5 22

R438 EU

AMP_SDA

K5

+1.10V_VDDC

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

AVDD_PLL

GND_17

VDDP

GND_18 GND_19

AVDD_DMPLL

GND_20

AVDD_NODIE

GND_21 GND_22

TEST

GND_23 GND_24

J8

4V

4V

C4006 0.1uF

C4000 0.1uF

4V C4005 0.1uF

GPIO36

LVA0P

GPIO37

LVA0M

GPIO38

LVA1P

GPIO39

LVA1M

GPIO40

LVA2P

GPIO41

LVA2M

GPIO42

LVACKP

GPIO45

LVACKM

GPIO46

LVA3P

GPIO49

LVA3M

GPIO50

LVA4P

GPIO51

LVA4M

GPIO52 GPIO53

LVB0P

GPIO54

LVB0M LVB1M

AB3 22 EU

AC4

AC24 AD25 AD24 AE24 AC23 AE23 AD23 AC22 AD22 AC21 AD21

RXA4+

L24

RXA4-

M8

RXA3+

M12

RXA3-

M13

RXACK+

M14

RXACK-

M15

RXA2+

M17

RXA2-

GPIO73

LVB2P

GPIO74

LVB2M LVBCKP LVBCKM LVB3P LVB3M LVB4M

W24 W25 W23 Y25 Y24 Y23 AA24 AA23 AB24 AB25 AB23

M18

RXA1+

M19

RXA1-

M24

RXA0+

N7

RXA0-

N13 N14

V23

LVB1P

R468

L20

AC25

LVB4P C4000,C4005,C4006 IS CAP FOR REPAIR SHOULD BE BOTTOM SIDE

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

J5

DSUB_DET

SCART1_MUTE

C4002 SHOULD NEAR MAIN IC

J7

AV2_DET

SC_RE1 4V

4V

0.1uF

0.1uF C492

0.1uF 4V UCC

UCC

DECAP FOR SOC (HIDDEN - UCC) UCC READY READY READY

C493

VDDC : 2026mA

C491

0.1uF NON-UCC C490

0.1uF NON-UCC

0.1uF NON-UCC C487

C484

0.1uF NON-UCC

0.1uF NON-UCC C482

C480

C478

C472-*1 1uF DUP_DVB DUP_AT C474 0.1uF

DUP_AT C472 1uF

1uF

10uF C465

10uF C455

10uF

C467-*1 1uF DUP_DVB

0.1uF NON-UCC

VDDC 1.05V

+1.10V_VDDC

C467

DUP_DVB

B7

RF_SWITCH_CTL

C457

0.1uF

READY

DECAP FOR SOC (HIDDEN - UCC)

C4002

0.1uF NON-UCC

0.1uF NON-UCC C441

DUP_DVB

10uF

L401-*1 CB1608UA121T

C440

L400-*1 CB1608UA121T

C401 0.1uF

DUP_AT

C434

DUP_AT

C431

L400 BLM18PG121SN1D

0.1uF

+3.3V_ST

C435 10uF

L401 BLM18PG121SN1D

C438

AVDD_NODIE:7.362mA AVDD_NODIE

0.1uF NON-UCC

VDD33

+3.3V

E6 H6

MODEL_OPT_1

STby 3.3V

GND_16

RXB4+

N15

RXB4-

N16

RXB3+

N17

RXB3-

N18

RXBCK+

N19

RXBCK-

N20

RXB2+

N25

RXB2-

P13

RXB1+

P14

RXB1-

P19

RXB0+

P21

RXB0-

GP4_S7LR MAIN

P24

GND_25 GND_26

V4

L407 BLM18SG121TN1D

L407-*1

W4

DECAP FOR SOC (HIDDEN - UCC)

C477 0.1uF

C453 IS CAP FOR REPAIR SHOULD BE BOTTOM SIDE

GND_15

GND_EFUSE

DUP_AT

C453 0.1uF 4V

AVDD_DVI_USB_MPLL

K8

+3.3V

IC400 LGE2111B

L406 BLM18PG121SN1D

READY

0.1uF

C402 0.1uF

C432

R403 100K

DECAP FOR SOC (HIDDEN - UCC)

DECAP READY FOR TEST

DUP_AT

SOC_RESET D400 BAW56 GEANDE

L406-*1 CB1608UA121T AVDD25_PGA DUP_DVB

AVDD_MIU DUP_DVB L402 BLM18PG121SN1D

C497 22uF 16V D400-*1 KDS181

AVDD_DDR0:55mA

W7

READY C4001 0.1uF 4V

UCC C489 0.1uF 4V

C485 0.1uF NON-UCC

C446-*1 1uF DUP_DVB

GND_14

W5

DUP_AT

L402-*1 CB1608UA121T

AVDD_AU33

Y6

AVDD2P5

+2.5V

W6

GND_12 GND_13

AA6 VDD33

GND_10 GND_11

DVDD_NODIE L405-*1 CB1608UA121T

GND_8 GND_9

AB8 C496

GND_3 GND_4

AB1 AB2

GND_95 GND_96

AVDD2P5_DADC

1K

1K

PWM1

R472

1K

GND_83

VDDC_4

AVDD25_LAN R470

R459

VDDC_3

AA8

AVDD2P5

AUD_MASTER_CLK

U4 VCOM

M16

AUD_SCK

1K

TX

GND_82

J17

Boot from 8051 with SPI flash Secure B51 without scramble Secure B51 with scramble Boot from MIPS with SPI flash Boot from MIPS with SPI flash Boot from MIPS with SPI flash Secure MIPS without scramble Scerur MIPS with SCRAMBLE

SOC_RESET

GND_81

VDDC_2

J14 J15

(I2S_OUT_BCK,I2S_OUT_MCK,PAD_PWM1PAD_PWM0)

C471 0.1uF

C460 0.1uF

IRIN/GPIO4

BIN2M

*H/W opt : ETHERNET

R445 49.9

AV/SC1_DET C6

BIN2P

R444 49.9

R441 49.9

GND_80

VDDC_1

DVDD_DDR

AVDD_MIU

1’b0 1’b1

R19 AVDDLV

P18

+1.10V_VDDC

+3.3V

RN

B1

IC400 LGE2111B

for SERIAL FLASH

PWM1/GPIO67

T22

KEY1

TP

COMP1_DET

R481

RL_ON

D5

PWM0/GPIO66

U23

SC_RE2

RP

C3

/PF_WP

AA10

DDCA_DA/UART0_TX

F6

C2

BUF1_FE_TS_SYN BUF1_FE_TS_DATA[0-7]

Internal demod out

BUF1_FE_TS_DATA[4]

AA13

PM_SPI_SDO/GPIO3

V24

NON_OS

0.047uF

BUF1_FE_TS_CLK

AC14

L5 GPIO_PM[9]/GPIO15

PM_SPI_SCK/GPIO1

Y22

COMP2_DET

R463

C406

CI_TS_DATA[7]

AA22

COMP2_L_IN COMP2_R_IN

R461

68

CI_TS_DATA[6]

AB14

DDCA_CK/UART0_RX

DUP_DVB

CVBSOUT2 R414

CI_TS_DATA[5]

AC13

+1.10V_VDDC

BLM18SG121TN1D

T7 L421

CI_TS_DATA[4]

AE12

from CI SLOT

PM_SPI_SCZ1/GPIO_PM[6]/GPIO12

UART1_RX/GPIO44

CVBS2

DTV/MNT_VOUT

PM_UART_RX/GPIO_PM[5]/GPIO11

GPIO_PM[8]/GPIO14

AA21 22

CI_TS_DATA[3]

AB11

J4 GPIO_PM[4]/GPIO10

UART2_TX/GPIO65

R466

CI_TS_DATA[2]

AE11

M5

PCMWAIT_N/GPIO100

PCM2_WAIT_N/GPIO133

U25

I2C_SCL

CI_TS_DATA[1]

W9

Y9

AB21

KEY2

AB9

TS1VALID/GPI96

PCMADR6/GPIO102

PCM2_CD_N/GPIO135

U24

I2C_SDA

for SYSTEM EEPROM (IC104)

AD11

GPIO_PM[2]/GPIO8

E4

SCART1_Rout

C456-*1 1uF DUP_DVB

TS1CLK/GPIO98

PCMADR5/GPIO101

PCM2_RESET/GPIO134 UART_RXD

CI_TS_DATA[0]

AB13

PCM2_IRQA_N/GPIO132

Y20

EU

PC_R_IN

DUP_AT

TS0DATA7/GPIO84

PCM2_CE_N/GPIO131

AB22

R455

PM_TXD

AB5

Y5

PCMADR2/GPIO122

AA20 Y21

PC_L_IN

C466 10uF

TS0DATA6/GPIO83

PCMCD_N/GPIO130

AA17

AV/SC1_R_IN

C463 0.1uF

PCMADR1/GPIO124

NF_WEZ/GPIO140

AD20

USB1_OCD

AV/SC1_L_IN

C456 1uF

TS0DATA5/GPIO82

AB12

TS1DATA7/GPIO95

AD18

SCART1_Lout

C454 4.7uF

PCMADR0/GPIO125

PCMREG_N/GPIO123

AD19

22

PM_RXD

2.2uF

L404

TS0DATA3/GPIO80

PCMADR7/GPIO103

AC19

R454

AUD_SCK

T5

0.047uF

AA19

/PCM_CE

AUD_MASTER_CLK AUD_LRCH AUD_LRCK

A3

RIN2M

SOGIN2 A_DEMODE R421 33

AE17

PCM_A[12]

UART_TXD

A2

RIN2P

V2

AC15

PCM_A[11]

PCMDATA7/GPIO116

AC17 /PCM_IRQA

I2S_I/F

TN

U2

PCM_A[10]

TS0DATA2/GPIO79

CI_TS_DATA[0-7]

AC11

B2

GIN1M

W1

33

AD17

TS0DATA1/GPIO78

PCMDATA6/GPIO117

PCMADR4/GPIO99

/PCM_IOWR

R457 10K

to delete CI or gate for

B8

AA9

RIN1P

SOGIN1

R416

AB18

PCM_A[9]

TS0DATA0/GPIO77

PCMDATA5/GPIO118

E5

P_SCL

22

R473

AUVRP

VSYNC1

P3

R417 R418

COMP2_Pb+

0 33

1000pF

B9

AA4

HSYNC1

N3

PCM_A[8]

SUB_SCL

AUVRM AUVAG

R3

R433

SC1_SOG_IN COMP2_Pr+

0.047uF

Y19 AC20

AE14

1K

CVBS In/OUT

33

R432 R434

SC1_B+/COMP1_Pb+

COMP2

SCART1_RGB/COMP1

R431

SC1_R+/COMP1_Pr+

AE20

PCM_A[6] PCM_A[7]

PCMDATA4/GPIO119

PCMADR3/GPIO121

SUB_SDA

B10

AA5

BIN0M

T2

PCM_A[5]

EU

AB4

GIN0P

T3

SC1_ID

Y18

AUDIO OUT

RIN0M

SOGIN0

SC1_FB

PCM_A[4]

RGB_DDC_SDA AUL1

M1

AD16

AUDIO IN

CEC/GPIO5

DSUB_VSYNC

DSUB

D_RX1P

AB16

PCM_A[3]

D2

A9

HOTPLUGD/GPIO22

CEC_REMOTE_S7

R406 10K

I2S_IN_WS/GPIO149

R6

DSUB_HSYNC

DSUB_B+

D_RX0P

PCM_A[2]

TS0SYNC/GPIO86

TS0DATA4/GPIO81

W16

DDCDD_CK/GPIO29

G4

HPD1

I2S_IN_SD/GPIO151

AA16

PCM_RST

DDCDD_DA/GPIO30

G6

DDC_SCL_1

I2S_IN_BCK/GPIO150

D_RXCN D_RX0N

G1

D1-_HDMI1

D_RX

PCM_A[1]

/PCM_IORD

+5V

30pF

C10

E2

Y17

/PCM_WE

/CI_CD2 E3 CK+_HDMI1 CK-_HDMI1

PCM_A[0]

/PCM_OE

AE9

DDCDC_CK/GPIO27

AC16

TS0VALID/GPIO85

PCMDATA2/GPIO128

AE18

TU_SDA

D1

C_RX2P

AB15

PCM_D[7]

/PCM_REG

B6

C_RX0N

DDCDC_DA/GPIO28

AC5

DDC_SCL_3

XOUT

C_RX1N

AC8

D2+_HDMI3

C_RXCN C_RX0P

AC6

D0-_HDMI3 D1+_HDMI3

XIN

C488 0.047uF 25V H_NIM

R449-*1 0

TU_SCL

AE2 AE4

C_RX

AD14

PCM_D[6]

PCMDATA1/GPIO127 PCMDATA3/GPIO120

IF_AGC_MAIN

AE3

DDCDA_CK/GPIO23

PCM_D[5]

PCM_A[14]

100

R449

IF_AGC

DDCDA_DA/GPIO24

F5

DDC_SCL_2

DUP_DVB

A_RX2N

F4

HPD2

AD3

H_NIM R448 10K

H_NIM C470 0.1uF

AC2

A_RX2P

K2

D2-_HDMI2 DDC_SDA_2

SIFM

A_RX1N

K3

D2+_HDMI2

A_RX1P

1M

D1-_HDMI2

SIFP

AE15

Y11

1K

K1

L403-*1 CB1608UA121T

AD1

A_RX0N

NON_A_DEMODE AGC 1.25V 100 OHM SERIAL A_DEMODE 0ohm

H_NIM

IM

A_RX0P

J2

D0-_HDMI2 D1+_HDMI2

L403 BLM18PG121SN1D

AD2

AD15

PCM_D[4]

TS0CLK/GPIO87

OS

J1

D0+_HDMI2

IP

R437

CK-_HDMI2

AC3 A_RX

Y16

PCM_D[3]

CI_TS_VAL CI_TS_SYNC

AA11 PCMDATA0/GPIO126

R462

MAIN H3 IC H2

CK+_HDMI2

PCM_D[2]

PCM_A[0-14]

A_DEMODE

A_DEMODE

IC400 LGE2111B

AB17 MAIN IC AB19

PCM_D[1]

H_NIM

H_NIM

R410

2D R405

CI_TS_CLK PCM_D[0]

Close to MSTAR R442

1K

RF_SWITCH_CTL 1K

PIN NO.

IC400

PCM_D[0-7]

GND_85

GND_27

GND_54

GND_28

GND_55

GND_29

GND_56

GND_30

GND_57

GND_31

GND_58

GND_32

GND_59

GND_33

GND_60

GND_34

GND_61

GND_35

GND_62

GND_36

GND_63

GND_37

GND_64

GND_38

GND_65

GND_39

GND_66

GND_40

GND_67

GND_41

GND_68

GND_42

GND_69

GND_43

GND_70

GND_44

GND_71

GND_45

GND_72

GND_46

GND_73

GND_47

GND_74

GND_48

GND_75

GND_49

GND_76

GND_50

GND_77

GND_51

GND_78

GND_52

GND_79

GND_53

R23 T23 U5 U6 V11 V15 V16 V17 V18 V19 V20 V21 W11 W15 W17 W18 W20 W21 W22 Y7 AA7 AB6 AB7 A15 A17 A20 B14 B16 B18 B21 C11 C12 C13 C20 C23 C25 D23 E17 E18 E20 E23 F18 G10 G12 G15 G16 G19 G20 G24 H10 H12 H13 H14 H15 H16 H19 H25 J12 J13 J19 J20 J24 K12 K13 K14 K15 K18 K19 K25 L8 L12 L13 L14 L15 L18 L19

2011-10-20 4

6

LGE Internal Use Only

+3.3V_ST

A1

A2 KDS184 D500-*1

+5V

C

DUP_AT

LVDS

Key/IR

NAND Flash 1GBit

IC504 H27U1G8F2BTR-BC +3.3V

+5V

R538 4.7K

R539 4.7K R519 100

SUB_SCL

DUP_DVB

C520 10pF 50V

R512 4.7K

R577 4.7K A2

R/B

ZD507 ZD506 DUP_DVB

7

1

2

2

3

3

R536

22

4

4

R537

22

5

8

VCC_1

UART_RXD

VSS_1

UART_TXD NC_9

5 6

NC_10

7

7

8

9

10

9

11

10

14

RXA0RXA0+ RXA1RXA1+

ZD505 DUP_DVB

22 23

ZD506-*1 ZD502-*1 ZD501-*1

24

ZD500-*1

5.6B DUP_AT

WE WP

46

4

45

5

44

6

43

7

42

8

41

9

40

10

39

11

38

12

37

13

36

14

35

15

34

16

33

17

32 31 30

NC_29 NC_28 NC_27 PCM_A[0-7] NC_26

AR518 22

I/O7

PCM_A[7]

I/O6

PCM_A[6]

I/O5

PCM_A[5]

I/O4

PCM_A[4]

NC_25 NC_24 C554 10uF

NC_23 VCC_2 VSS_2

C555 0.1uF

NC_22 NC_21 NC_20

AR519 22

I/O3

PCM_A[3] IC504-*1 K9F1G08U0D-SCB0

I/O2

SS NC_1

PCM_A[2]

NC_2 NC_3

I/O1

PCM_A[1]

NC_4 NC_5 NC_6

NC_11

29

20

I/O0

R/B

PCM_A[0]

RE CE

15

R556 3.3K

16

R567 1K

NC_12

18

28

21

NC_13

17 RXACKRXACK+ RXA3RXA3+ RXA4RXA4+

47

3

19

/PF_WP

14 RXA2RXA2+

2

18

/PF_WE

13

27

22

NC_19

NC_7 NC_8 VCC_1 VSS_1

NC_18

NC_9 NC_10 CLE

NC_14

26

23

19

NC_17

ALE WE WP

NC_15

20

24

25

NC_16

NC_11 NC_12 NC_13

21

NC_14 NC_15

1

48

2

47

3

46

4

45

5

44

6

43

7

42

8

41

9

40

10

39

11

38

12

37

13

36

14

35

15

34

16

33

17

32

18

31

19

30

20

29

21

28

22

27

23

26

24

25

NC_29 NC_28 NC_27 NC_26 I/O7 I/O6 I/O5 I/O4 NC_25 NC_24 NC_23 VCC_2 VSS_2 NC_22 NC_21 NC_20 I/O3 I/O2 I/O1 I/O0 NC_19 NC_18 NC_17 NC_16

22

25

5.6B DUP_AT

ALE PF_ALE

12

18 19

/PF_CE1

11

15

17

CLE

8

9

21

5.6B DUP_AT

C550 0.1uF

6

20

5.6B DUP_AT

CE /PF_CE0 NC_7

1

16

ZD507-*1

47K R578

RE /PF_OE

NC_8

C547 0.1uF 16V

ZD505-*1 ZD504-*1

NC_6

R568 4.7K

/F_RB E Q500 MMBT3904(NXP)

P503 TF05-51S

6

13

5.6B DUP_AT

C

P500 104060-8017

5

12

5.6B DUP_AT

R513 4.7K A1

ZD502

R514 22

+3.3V_ST

ZD503-*1

R565 1K

C B

DUP_AT

C522 10pF R520 50V 100READY C523 10pF 50V READY

SUB_SDA

NC_5

2K R579

4

ZD503 DUP_DVB

+3.3V_ST

ZD500

LED_RED

D500 MMBD6100 DUP_DVB

3 C534 0.1uF 16V

KEY2 C535 0.1uF 16V

NC_4

2

DUP_DVB

R516 100

NC_3

B

48

1

NC_2

C

ZD504 DUP_DVB

KEY1

+3.3V

LD500

DUP_DVB

R542 10K R517 100

DUP_DVB

1 C517 10pF 50V

R540 10K

DUP_DVB 2SC3052 Q500-*1

5.48VTO5.76V

+3.3V_ST

ZD501

IR

NC_1 E

R515 4.7K R518 100

10V

P501 12507WS-08L USA

23

26

5.6B DUP_AT

5.6B DUP_AT

HD

24 27 28 29 30

RXB0RXB0+ RXB1RXB1+

25 26 27 28

31 32 33

30

34 35 36 37 38 39 40

31 32

RXBCKRXBCK+ RXB3RXB3+ RXB4RXB4+

33 +3.3V_ST

+3.3V_ST +3.3V_ST

34

IC505 W25Q80BVSSIG

35 36

41

37

42

38

43

39

44

40

45 46

SERIAL FLASH 8MBit

29

RXB2RXB2+

FHD

MX CS#

RXA0RXA0+

42

RXA1-

43

48

IC505-*1 MX25L8006EM2I-12G

41

47

49

44

50

45

51

46

R564 10K

SO/SIO1

R569 4.7K READY

CS

/SPI_CS 1

8

2

7

3

6

4

5

DO[IO1]

HOLD#

SPI_SDO WP#

GND

RXA1+

1

8

2

7

3

6

4

5

C556 0.1uF

VCC

VCC

HOLD[IO3]

SCLK

%WP[IO2]

SI/SIO0

/FLASH_WP

RXA2-

GND

RXA2+

CLK SPI_SCK R575 DI[IO0] 33 SPI_SDI

47

52

48

RXACK-

49

RXACK+

50

RXA3-

51

RXA3+

52

RXA4-

53

RXA4+

54 55 56

RXB0-

57

RXB0+

58

RXB1-

59

RXB1+

60

+3.3V

61

RXB2-

62

RXB2+

63

IC503-*1 R1EX24256BSAS0A

64

RXBCK-

65

RXBCK+

66

RXB3-

67

A0’h

EEPROM 1MBit

RXB3+

68

RXB4-

69

RXB4+

Renesas_IC503 A0 1 A1

A2

VSS

8

2

7

3

6

4

5

C552 0.1uF

VCC

WP

IC503 AT24C256C-SSHL-T

SCL

SDA

A0

1

8

2

7

VCC

70 71

A1

72

WP

ATMEL_IC503

73

A2

3

6

SCL

R573 22

SDA

R574 22

I2C_SCL

74 75 76 77

P_SDA

GND

4

5

I2C_SDA

DISP_EN

78

P_SCL PC_SER_DATA

79

PC_SER_CLK

80 81

Addr:10101--

HD EEPROM 8KBit +3.3V

IC502 CAT24C08WI-GT3-H-RECV(TV)

R563 4.7K READY

NC_1

1

NC_2

2

A2 3 VSS

4

8

VCC

7

WP

6

SCL

READY

5

R570 4.7K READY

SDA

R571 22 READY R572 22 READY

I2C_SCL I2C_SDA

* LCI: LVDS Connection Indicator

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

GP4_S7LR Memory.LVDS,IR

2011-10-20 5

6

LGE Internal Use Only

+3.3V Multi

P_17V

VOUT

1

C604-*1 1uF 10V DUP_AT

1

C601 0.1uF 16V

C600 10uF 10V

GND

2

GND

C604 1uF 6.3V DUP_DVB

VOUT

IN R612 1 C612 10uF 6.3V

L604 120-ohm 2A DUP_AT

ADJ/GND C671 10uF 10V DVB_T2

C682 0.1uF 16V DVB_T2

R1

R2

C617 10uF 6.3V FNIM

IC604 R2 AZ1117BH-ADJTRE1

INPUT

OUT

R618 240 FNIM

L604-*1 CB1608UA121T

R620 1 FNIM C625 10uF 6.3V FNIM

ADJ/GND

OUTPUT C627 10uF 6.3V

DCON_EN

L606 CIS21J121 +5V

EN2

PGOOD

24

GND_2

25

GND_3

26

GND_4

27

GND_5

28

IC605 TPS65253RHDR

R630 3K 1% R631 390K 1% R621 1 C631 10uF 6.3V

Vout=1.25*(1+R2/R1)

15

VIN2

12

LX2_2

11

LX2_1

10

LX1_2

9

LX1_1

8

VIN1

C609 3300pF READY

R2 R656 47K 1% C656 22uF 16V

C651 22uF 16V

L607 NR5040T3R3N

R657 43K 1%

C666 0.022uF 16V +1.5V_DDR

R1 L608 NR5040T3R3N

7

+1.10V_VDDC C683 22uF 16V C653 10uF 25V

C654 10uF 25V

C652 0.047uF 25V

C657 22uF 16V

R653 6.8K 1%

C661 0.022uF 16V

R654 51K 1%

R1

R655 100K 1%

R2

+1.8V_TU

R1

DUP_DVB

DUP_AT

R648 120K

RLIM2

13

Vout=1.25*(1+R2/R1)

DCON_EN

2

3

+3.3V_TU

+3.3V

+1.25V_TU IC602 AP1117EG-13 FNIM

R615 1 FNIM

VIN 3

VIN

+3.3V

DUP_DVB L613 120-ohm 2A DVB_T2

220 100 R614 R613 5% 5%

IC601 TJ3940S-2.5V-3L

IC600 AP2121N-3.3TRE1

+2.5V_TU

+2.5V

+3.3V +3.3V_ST

16

23

[EP]GND

L613-*1 CB1608UA121T +5V_ST

SS2

GND_1

BST1

3.3V_TU /1.8V_TU

17

BST2

1

1.25V_TU

2.5V Multi/2.5_TU

CMP2

14

Vout=0.765*(1+R1/R2)

3.3Vst

FB2

22

6

C626 3300pF 50V

R670 4.7 READY C655 0.047uF 25V

V3V

5

C630 0.1uF 16V

EN1

C629 10uF 16V

R649 33K

C624 1uF 10V

C650 10uF 16V

GND

4

SS

18

L605 NR5040T2R2N 2.2uH

RLIM1

5

C628 4700pF 50V

R647 100K

6

4

SW

0.01uF

3

VBST

19 R2 R619 17.4K 1%

C634 10uF 16V

C649

VREG5

C632 4.7uF 10V

+3.3V

19

C607 0.1uF 16V

7

VIN

3

18

2

8

SS1

17

VFB

AC_DET

1

LOW_P

5V_ON

EN R1 R617 59K 1%

20

16

C610 0.1uF 16V

2

14

15

C608 10uF 10V

+5V_ST

CMP1

13

RL_ON

ERROR_DET

R609 100

C606 0.1uF 16V

DUP_DVB

R634 56K

V7V

12

IC603 TPS54327DDAR [EP]GND

R661 10K

21

10

11

+5V

R650 33K

THERMAL 29

8

9

DUP_DVB L600 120 DUP_AT

FB1

7

C636

R639 3300pF 10K

ROSC

6

0.01uF

R635 3300pF 10K

4

5

C621 0.1uF 50V

C645

R600 10K

2

3

C642

L606-*1 MLB-201209-0120P-N2 C620 10uF 25V

9

+3.3V_ST

1

L600-*1 MLB-201209-0120P-N2

P_17V

THERMAL

P600 SMAW200-H18S1

1.5V DDR / 1.24V Core

DCON_EN

Power Wafer

R662 56K

C611 3300pF 50V READY R666 4.7 READY

Vout=0.8*(1+R1/R2)

Audio AMP

L601

500-ohm

+3.3V

EMI GND R608 0

R628 10K READY C

READY

VDD_DIG_1 GND_DIG_1

AC_DET 22 R638

R625

PWRDN

2.2

VDD_PLL R629 2K

C633 0.1uF 16V R626 0 AUD_MASTER_CLK

READY AUD_SCK READY AUD_LRCK READY AUD_LRCH READY

C637 4700pF 50V

C647 680pF 50V

FILTER_PLL GND_PLL

C635 22pF 50V C639 22pF 50V C640 22pF 50V C644 22pF 50V

22 R640 22 R641 22 R642 22 R643

XTI BICKI LRCKI SDI

AMP_RESET_N 22 R644 R623

2K

RESET INT_LINE

R646 22

SDA

AMP_SDA R624

2K AMP_SCL

SCL R633 10K C638 0.1uF 50V C687 330pF 50V

C684 330pF 50V

C685 330pF 50V

C686 330pF 50V

GND_DIG_2 C646 0.1uF 50V

VDD_DIG_2

21

16

22

15

23

14

24

13

25

12

26

11

27Close-by

Close-by 10

28

9

29

8

30

7

Close-by 31

6

32

5

33 34

THERMAL

R645 22

17

4 3

35

2

36 Close-by

1

OUT3A/FFX3A

R605 0

EMI_GND1

OUT3B/FFX3B R606 0

CONFIG C660 0.1uF 50V

VDD

R604 0

GND_REG OUT1A GND1

L609 10.0uH

C662 1uF C663

VCC1

25V C669 0.1uF 50V 330pF 50V

C672 0.22uF 50V

L610 10.0uH

C674 0.22uF 50V

C678 1000pF 50V

C675 0.22uF 50V

C679 1000pF 50V

4

3

OUT1B OUT2A

C664 1uF C665

C670 25V 330pF

0.1uF 50V

VCC2

L612 10.0uH

GND2 P_17V

OUT2B VCC_REG

L611 10.0uH

50V

C659 0.1uF 50V

C667 0.1uF 50V

2

C673 0.22uF 50V

C676 0.22uF 50V

C680 1000pF 50V

C677 0.22uF 50V

C681 1000pF 50V

EMI_GND2

R602 0

1

SMAW250-H04R P601

C643 0.1uF 50V

18

20

R686 39

TWARN/OUT4A

19

R688 39

EAPD/OUT4B

39 R685

Q600 MMBT3904(NXP) E READY R637 0

39 R687

B

READY

37

R627 10K AMP_MUTE

R607 0

R636 0

R601 0

EMI_GND3

R603 0

EMI_GND4 GND

C668 68uF 35V

VSS TEST_MODE SA GND_SUB

[EP]GND

STA368BWG IC606

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

GP4_S7LR Power,AMP

2011-04-01 6 LGE Internal Use Only

C1219-*1 1uF DUP_DVB

C1238-*1 1uF DUP_DVB

C1241-*1 1uF DUP_DVB

1uF DUP_AT

1uF DUP_AT C1238

1uF DUP_AT C1219

10uF

C1218

C1251

DUP_AT L1202-*1 CB2012PK501T

1uF DUP_AT C1241

R1227

OS 1K 1% 0.1uF

C1250 OS 1% 1K

C1249

OS

OS 1000pF

R1225

C1218-*1 1uF DUP_DVB

L1202 CIC21J501NE

R1228

R1224

OS 1K 1% 0.1uF

C1248 OS 1K 1%

C1247

OS

OS 1000pF

AVDD_DDR0

+1.5V_DDR

DUP_DVB

CLose to Saturn7M IC

CLose to Saturn7M IC

CLose to DDR3

AVDD_DDR0

B-MVREFDQ

B-MVREFCA

A-MVREFCA

1000pF

0.1uF C1204

1% 1K

R1205

A-MVREFDQ

C1203

1000pF

0.1uF C1202

C1201

AVDD_DDR0

1K 1%

R1204

AVDD_DDR0

1K 1% 1%

R1202

1K

R1201

AVDD_DDR0

CLose to DDR3

EAN61828901

EAN61828901

IC1201 H5TQ1G63DFR-H9C

IC1202 H5TQ1G63DFR-H9C

IC400 LGE2111B

DDR_1333_HYNIX

DDR_1333_HYNIX

A3

VREFDQ

A4 A5

L8

A6

ZQ 240 1%

A7 A8

B2

C1208 C1210 C1211 C1212 C1213 C1214 C1215 C1216 OS

D9

0.1uF

G7

0.1uF

K2

0.1uF

K8

0.1uF

N1

0.1uF

N9

0.1uF

R1 R9

0.1uF

A9

VDD_1

A10/AP

VDD_2 VDD_3

A11

VDD_4

A12/BC

F1 H2 H9

L9 T7

A-MA14

VDD_8 BA0

J2 J8 M1 M9 P1 P9 T1 T9

CK

VDDQ_3

CK

E2 E8 F9 G1 G9

AR1224

22

A_MA12

A-MA13

A-MBA1

A_MBA1

A-MA9

A-MA10

A_MA10

A-MA0

A-MCKE

A_MCKE

A-MWEB

AR1223

VDDQ_5

AR1222

ODT

VDDQ_7

RAS

VDDQ_8

CAS

T7

NC_6

N7

A9 DQSU

B7

VSS_1

DQSU DML

D3

A-MA12

T3

VSS_5 VSS_7

J2 J8

VSS_6

F7

DQL1

F2 F8 H3

A-MA13

E1 G8

VSS_4

DMU DQL0

E3

H8 G2

VSS_9 VSS_10

DQL4

VSS_11

DQL5

VSS_12

M9 P1 P9 T1

B1 VSSQ_1

DQU0

C2

A3

A-MBA1

M3

A-MBA2

K7 K9

VSSQ_3 VSSQ_4

E2

VSSQ_5

DQU4

VSSQ_6

DQU5

VSSQ_7

DQU6

VSSQ_8

DQU7

VSSQ_9

E8 F9 G9

SS_1G_1600

N3 P7

C1209

P3 N2 P2 R8 R2 T8

0.01uF 50V

R3 L7 R7 N7 T3

M3

VREFCA

A2

K3 L3

L8 ZQ

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_7

BA0

VDD_9

VDD_6 VDD_8

VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5

CS

VDDQ_6

ODT

VDDQ_7

RAS

VDDQ_8

CAS

VDDQ_9

NC_2 NC_3 NC_4

DQSL

VSS_2 VSS_3

DML

VSS_4

DMU

VSS_5 VSS_6

E3 F7 F2 F8 H3 H8 G2 H7

DQL0

VSS_7

DQL1

VSS_8

DQL2

VSS_9

DQL3

VSS_10

DQL4

VSS_11

DQL5

VSS_12

C3 C8

A2 B8

A-MRESETB

A3

A_MCKE

A8

DQSL

H9

A_MODT

J9 L1 L9

A_MRASB

T7

B3

A_MCASB

E1 G8 J2 J8 M1

A_MWEB

M9 P1

DQSU

VSS_2

DQSU

P9

B1 VSSQ_1

DQU0

VSSQ_2

DQU1

VSSQ_3

DQU2

VSSQ_4

DQU3

VSSQ_5

DQU4

VSSQ_6

DQU5

VSSQ_7

DQU6

VSSQ_8

DQU7

VSSQ_9

B9 D1

A_MRESETB

D8 E2 E8

SS_1G_1333

VSS_3

P8

E7

VSS_4

DML

VSS_5

DMU

P2 R8 R2

A-MDML

D3

T8 R3 L7 R7 N7

A-MDMU

T3

A0

M3

DQL0

VSS_7

DQL1

VSS_8

DQL2

VSS_9

DQL3

VSS_10

DQL4

VSS_11

DQL5

F7

K1

F2

DQU0

VSSQ_3

DQU1

VSSQ_4

DQU2

VSSQ_5

DQU3

VSSQ_6

DQU4

VSSQ_7

DQU5

VSSQ_8

DQU6

VSSQ_9

DQU7

VDD_3

A12/BC

VDD_4 VDD_5 VDD_6

NC_5

VDD_7

BA0

VDD_9

VDD_8

J3 K3 L3

CK

VDDQ_3 VDDQ_4

CS

VDDQ_6 VDDQ_7

RAS

VDDQ_8

CAS

VDDQ_9

DQSL

H3

D3

H8

F7 F2 F8

A-MDQL5

G2

DML

H8 G2 H7

VSS_1 VSS_2 VSS_4

DMU

VSS_5

DQL0

VSS_7

VSS_6 DQL1

VSS_8

DQL2

VSS_9

DQL3

VSS_10

J7

C1

K7

DQL4

VSS_11

DQL5

VSS_12

H7

C2 A7 A2

A-MDQL7

B8 A3

DQU0

C9

K9

F1 H2 H9

K1 J3 K3 L3

J9

B3

J2

D3 E3

M9

F7

P1

F2

P9

F8

T1

H3

T9

H8 G2

VSSQ_2

DQU1

VSSQ_3 VSSQ_4 VSSQ_5

DQU4

VSSQ_6

DQU5

VSSQ_7

DQU6

VSSQ_8

DQU7

VSSQ_9

B9 D1

C8

E2

C2

E8

A7

F9

A2

G1

B8

G9

A3

C3 C8 C2

AR1219

A-MA1 A-MA14

22

A2 B8 A3

A_MA1 A_MA14

A-MBA2 A-MA3

VSS_8 VSS_9 VSS_10 VSS_11

DQL5

VSS_12

A-MDQL6

P1 P9 T1

A-MDQL7

T9

DQL6 VSSQ_1 DQU0

VSSQ_2

DQU1

VSSQ_3

DQU2

VSSQ_4

A_DDR3_A13

B_DDR3_A13

A_DDR3_A14

B_DDR3_A14

B12 G11 B13

G25 H20 D25

A_DDR3_BA0

B_DDR3_BA0

A_DDR3_BA1

B_DDR3_BA1

A_DDR3_BA2

B_DDR3_BA2

K22 E25

B-MA11

B_MA11

B-MA12

B_MA12

B17 C17

B_MA13 B_MA14 B_MBA0 B_MBA1

F13

B_DDR3_MCLK

A_DDR3_MCLKZ

B_DDR3_MCLKZ

A_DDR3_MCLKE

B_DDR3_MCLKE

H24 M20

B-MCKB

B-MBA0

B-MCK

B-MBA1

0.01uF 50V

B_MCKE

B-MBA2

DQU3 DQU4

VSSQ_5 VSSQ_6

DQU5

VSSQ_7

DQU6

VSSQ_8

DQU7

VSSQ_9

E2 E8 F9

A-MDQU0

G1 G9

AR1206

22

B-MA9

A_MA0

B-MA10

B_MA10

B-MA0

A_MWEB

B-MCKE

B_MCKE

B-MWEB

AR1212

22

B_MA11

AR1202

22

B-MODT

B_MODT

AR1204

22

B-MA1 B-MA14

R7 N7 T3

A8

M3

A10/AP

VDD_2

A11

VDD_3

A12/BC

VDD_4

B-MCKE

A11 B11 A12 E9

C24 A_DDR3_ODT A_DDR3_RASZ A_DDR3_CASZ A_DDR3_WEZ

B_DDR3_ODT

VDD_6

B_DDR3_RASZ B_DDR3_CASZ

B25 D24 F22

B_DDR3_WEZ

B-MODT

B_MRASB B_MCASB

AVDD_DDR0

B_MWEB

B-MRASB B-MCASB

G8

E21 A_DDR3_RESET

B_DDR3_RESET

B_MRESETB

R1232 10K

B-MWEB

B22 C22

P25 A_DDR3_DQSL A_DDR3_DQSBL

B_DDR3_DQSL

A21 C21

N24 A_DDR3_DQSU A_DDR3_DQSBU

B_DDR3_DQSU

M23

B_DDR3_DQSBU

B20 D17

N23

B_DDR3_DQSBL

L23 A_DDR3_DQML

B_DDR3_DQML

A_DDR3_DQMU

B_DDR3_DQMU

A_DDR3_DQL0

B_DDR3_DQL0

A_DDR3_DQL1

B_DDR3_DQL1

R20

OS

B-MRESETB

B23 B19 A23 C19 B24 C18 A24 A18

P23

A_DDR3_DQL2 A_DDR3_DQL3 A_DDR3_DQL4 A_DDR3_DQL5 A_DDR3_DQL6 A_DDR3_DQL7

B_DDR3_DQL2 B_DDR3_DQL3 B_DDR3_DQL4 B_DDR3_DQL5 B_DDR3_DQL6

L25 R24 K23 T25 J23 T24 K24

B_DDR3_DQL7

D15 F17 F14 E16 D14 D16 E14 F16

N21 A_DDR3_DQU0 A_DDR3_DQU1

B_DDR3_DQU0 B_DDR3_DQU1

A_DDR3_DQU2

B_DDR3_DQU2

A_DDR3_DQU3

B_DDR3_DQU3

A_DDR3_DQU4

B_DDR3_DQU4

A_DDR3_DQU5

B_DDR3_DQU5

A_DDR3_DQU6

B_DDR3_DQU6

A_DDR3_DQU7

B_DDR3_DQU7

P22 L22 R21 P20 R22 M22 N22

K3 L3

VDDQ_2 VDDQ_3

CKE

VDDQ_4 VDDQ_5

RAS CAS

B-MDQSL B-MDQSLB

B-MDQSUB B-MDQSU B-MDML

B-MDQSUB

B-MDMU B-MDML B-MDQL0

B-MDMU

B-MDQL1 B-MDQL2 B-MDQL3 B-MDQL4 B-MDQL5 B-MDQL6 B-MDQL7

B-MDQL0 B-MDQL1 B-MDQL2 B-MDQL3 B-MDQL4 B-MDQL5 B-MDQL6

B-MDQU0

VDDQ_6 VDDQ_7 VDDQ_8

B-MDQL7

B-MDQU1 B-MDQU2

B-MDQU0

B-MDQU3

B-MDQU1

B-MDQU4

B-MDQU2

B-MDQU5

B-MDQU3

B-MDQU6

B-MDQU4

B-MDQU7

B-MDQU5

L8 ZQ

A8

B2

A9

VDD_1

A10/AP

VDD_2

A11

VDD_3

A12/BC

VDD_5 VDD_7

BA0

VDD_9

10uF 0.1uF

J3 K3

K8

OS C1229 OS C1230

0.1uF 0.1uF

N1

OS C1231

0.1uF

A1

VDDQ_6 VDDQ_7

RAS

VDDQ_8

CAS

VDDQ_9

G3

DQSL

OS C1232 OS C1233

0.1uF

A9 DQSU

VSS_1

DQSU

VSS_2

DML

VSS_4

DMU

OS C1234 OS C1235

0.1uF 0.1uF

OS C1236

0.1uF

F2 F8 H3 G2 H7

G8 J2

VSS_5

J8

VSS_6 DQL0

VSS_7

DQL1

VSS_8

DQL2

M1 M9 P1

VSS_9

DQL3

P9

VSS_10

DQL4

VSS_11

DQL5

VSS_12

T1 T9

DQL6 DQL7

B1 VSSQ_1

D7 C3 C8 C2 A7 A2 B8 A3

DQU0

B9

VSSQ_2

DQU1

D1

VSSQ_3

DQU2

VSSQ_4

DQU3

VSSQ_5

DQU4

D8 E2 E8

VSSQ_6

DQU5

VSSQ_7

DQU6

VSSQ_8

DQU7

VSSQ_9

F9 G1 G9

IC1202-*2 K4B1G1646G-BCK0

A8 N3 P7 P3

C1

N2 P8 P2 R8 R2

C9

T8 R3 L7 R7 N7

D2

T3

M8 A0

VREFCA

A1 A2

H1

A3

VREFDQ

A4 A5

L8

A6

ZQ

A7 A8

B2

A9

VDD_1

A10/AP

VDD_2

A11

VDD_3

A12/BC A13

M7

E9

M3

NC_5

VDD_7

BA0

VDD_9

VDD_8

F1

K9

K1 J3 K3 L3

VDDQ_2

CK

VDDQ_3

CKE

VDDQ_4

CS

VDDQ_6

VDDQ_5 ODT

VDDQ_7

RAS

VDDQ_8

CAS

VDDQ_9

WE RESET

NC_2 NC_3 NC_4

F3 G3

N9 R1 R9

A8 C1 C9 D2 E9 F1 H2 H9 J1

NC_1

T2

H9

K2 K8 N1

A1 VDDQ_1

CK

L2

H2

D9 G7

BA1 BA2

J7 K7

DQSL

J9 L1 L9 T7

NC_6

DQSL C7

J1 NC_2

VDD_4 VDD_5 VDD_6

M2 N8

D3

NC_4 DQSL

B3 E1

VSS_3

E7 D3

H8

0.1uF

T7

NC_6

DQSL C7

A9 DQSU

VSS_1 VSS_2 VSS_3

E7

NC_1

F3

L1 L9

NC_4

DQSU

RESET

J9

NC_2 NC_3

B7

T2

H2 H9 J1

RESET

E3

R9

D2 E9 F1

NC_1

T2

F3

F7

R1

A8 C1 C9

VDDQ_4 VDDQ_5

CS ODT

WE

B7

N9

R1 R9

VDDQ_1 VDDQ_2 VDDQ_3

L2 K1

L3

K2

K8 N1

BA2 CK CK CKE

OS C1228

N9

VDD_8 BA1

J7 K7 K9

G7

D9 G7 K2

VDD_6

M2

C1227

VDD_4

A13 A15

M7

VDDQ_9

WE

G3

H1 VREFDQ

A5 A6 A7

A1 VDDQ_1

CK

ODT

VREFCA

A1 A2 A3 A4

SS_1G_1600

NC_3

B-MDQSLB

D9

M8 A0

DML

VSS_4

DMU

VSS_5

DQL0

VSS_7

VSS_6

E3 F7 F2 F8 H3

J9

H8 G2 H7

DQL1

VSS_8

DQL2

VSS_9

DQL3

VSS_10

DQL4

VSS_11

DQL5

VSS_12

C3 C8 C2 A7 A2

L9 T7

NC_6

B8 A3

J2 J8 M1 M9 P1 P9 T1 T9

B1 VSSQ_1

D7

L1

B3 E1 G8

DQL6 DQL7 DQU0

VSSQ_2

DQU1

VSSQ_3

DQU2

VSSQ_4

DQU3

VSSQ_5

DQU4

VSSQ_6

DQU5

VSSQ_7

DQU6

VSSQ_8

DQU7

VSSQ_9

B9 D1 D8 E2 E8 F9 G1 G9

B-MA14

DQSL C7 B7

A9 DQSU

VSS_1

DQSU

VSS_2 VSS_3

E7 D3

DML

VSS_4

DMU

VSS_5 VSS_6

E3 F7 F2 F8 H3 H8 G2 H7

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5

VSS_7 VSS_8 VSS_9 VSS_10 VSS_11

C2 A7 A2 B8 A3

SS_1G_1333 SS_2G_1333

IC1202-*3 K4B1G1646G-BCH9

G8

N3 P7 P3

J2

N2 P8 P2 R8 R2

J8

T8 R3 L7 R7 N7

M1

T3

A0

M3

P7 P3 P8 P2

T8

A8

B2 VDD_1 VDD_2

A11 A12/BC

VDD_3 VDD_4 VDD_5 VDD_6

NC_5

VDD_7

BA0

VDD_9

VDD_8

K9

K1 J3 K3 L3

CK

VDDQ_3

CKE

VDDQ_4

CS

VDDQ_6

VDDQ_5 ODT

VDDQ_7

RAS

VDDQ_8

CAS

VDDQ_9

RESET

NC_4 DQSL

D3

F2

H8 G2 H7

VSS_1 VSS_2 VSS_4

DMU

VSS_5 VSS_7

VSS_6 DQL1

VSS_8 VSS_9

DQL3

VSS_10

DQL4

VSS_11

DQL5

VSS_12

DQU1

VSSQ_3

DQU2

VSSQ_4

DQU3

VSSQ_5

DQU4

VSSQ_6

DQU5

VSSQ_7

DQU6

VSSQ_8

DQU7

VSSQ_9

A7 A2

B9

B8 A3

DQU0

K2 K8 N1 N9 R1 R9

A1 VDDQ_1

CK

VDDQ_2 VDDQ_3

CKE

VDDQ_4

CS

VDDQ_6

VDDQ_5 ODT

VDDQ_7

RAS

VDDQ_8

CAS

VDDQ_9

NC_4

F3 DQSL

A8 C1 C9 D2 E9 F1 H2 H9 J1

NC_1 NC_2 NC_3

B3

J9 L1 L9 T7

NC_6

C7 B7

J2

D3

J8 M1

E3

M9

F7

P1

F2

P9

F8

T1

H3

T9

VSSQ_2 VSSQ_3 VSSQ_4

H8

VSSQ_5 VSSQ_6

DQU5

VSSQ_7

DQU6

VSSQ_8

DQU7

VSSQ_9

B9

C3 C8 C2 A7

F9

A2

G1

B8

G9

DML

VSS_4

DMU

VSS_5

DQL0

VSS_7

VSS_6 DQL1 DQL2

VSS_8 VSS_9

DQL3

VSS_10

DQL4

VSS_11

DQL5

VSS_12

A3

B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

DQL6 B1 VSSQ_1

D7

D1

E8

VSS_1 VSS_2 VSS_3

DQL7

D8 E2

A9 DQSU DQSU

E7

G2

DQU1 DQU3

D9 G7

BA1

CK

WE

H7

DQU2 DQU4

VDD_8

RESET

B1 VSSQ_1

D7 C3 C8 C2

VDD_7 VDD_9

T2

E1 G8

DQL6 DQL7

B1

NC_5 BA0

DQSL

DQL0 DQL2

K1 J3 K3

G3

VSS_3 DML

E3

F8

VSSQ_2

T7

B2

VDD_3 VDD_4 VDD_5 VDD_6

L2

L1

A9 DQSU DQSU

H3

DQU0

J9

A11 A12/BC

L9

NC_6

C7 B7 E7

DQL6 VSSQ_1

F1 H2

DQSL

T9

K9

D2

J1 NC_2 NC_3

F3

J7 K7

H9

L8

VDD_1 VDD_2

BA2

A8 C9

H1

ZQ

A7 A8 A9 A10/AP

M2

C1

E9

VREFCA

VREFDQ

A4 A5 A6

M7

R1 R9

M8 A0 A1 A2 A3

A13

L3 NC_1

T2

G3

N7 T3

M3

VDDQ_2

WE

T1

K2 K8 N1 N9

A1 VDDQ_1

L2

P9

L7 R7

N8

BA2

P1

R3

D9 G7

BA1

CK

R8 R2

A9

J7 K7

N2

L8 ZQ

A10/AP

M2

M9

N3

H1 VREFDQ

A4 A5 A6 A7

A13

N8

IC1202-*4 K4B2G1646C M8

VREFCA

A1 A2 A3

M7

F7

D7 C8

E1

VSS_12

DQL7

C3

B3

DQU0

VSSQ_2

DQU1

VSSQ_3

DQU2

VSSQ_4

DQU3 DQU4

VSSQ_5 VSSQ_6

DQU5

VSSQ_7

DQU6

VSSQ_8

DQU7

VSSQ_9

B9 D1 D8 E2 E8 F9 G1 G9

D1 D8 E2 E8 F9 G1 G9

B_MA7

22

B_MRESETB B_MA2

22

B_MCASB

B-MBA0

B-MA3

J3

N7

22

B-MCASB

B-MBA2

K1

L7 R7

N8

VDD_9

CK

CS

R3

AVDD_DDR0

M3

BA1

B-MDQSL

B-MDQSU

VDD_7 VDD_8

L2

B_MODT

VDD_5

BA2

K9

P2 R8 R2 T8

B2 VDD_1

BA0

P3 N2 P8

T3

A9

M2

IC1202-*1 H5TQ1G63DFR-PBC N3 P7

240 1%

A7

A13

N8

L8 ZQ

B_MA5

B_MBA0

AR1208

B_MA1

L7

A6

OS R1226

22

B-MA2

22

B_MA14

R3

B-MVREFDQ Hynix_1G_1600

A5

B_MA0

AR1225

B_MRASB

T8

H1 VREFDQ

A4

22

B-MRESETB

22

B-MRASB

R2

A3

B_MWEB

AR1209

B_MA8

R8

B-MVREFCA

B_MA13

AR1205

22

B-MA8

P2

A2

B_MA9

AR1210

22

B-MA11

P8

K7

B-MDQU7

AR1203

N2

M8 VREFCA

A1

J7

B-MDQU6

AR1207

P3

A0

NC_5

B_MBA2 B-MCK

P7

M7

OS C1240 H23

A_DDR3_MCLK

B-MA13

A-MDQU6

B_MBA1

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

B_DDR3_A12

B_MA10

A-MDQU7

B-MBA1

A_MA3

A_DDR3_A12

J22

B-MA10

B9

A-MDQU6

A_MA9

A_MBA2

B_DDR3_A11

G22

B_MA9

D1

A-MDQU5

B-MA13

A_MBA0

A_DDR3_A11

L21

B-MA9

D8

A-MDQU7

B_MA12

A_MRESETB

B_DDR3_A10

B_MA8

B1

A-MDQU5

AR1211

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

DQL1 DQL2 DQL3 DQL4

J2 J8 M1 M9

A-MDQU4

B-MA12

A_MA2

AR1215

VSS_6

A-MDQU3

A7

22

A-MBA0

VSS_4 VSS_5 VSS_7

A-MDQU4

B-MA7

A_MODT

DML DMU DQL0

A-MDQL5

B3 E1 G8

A-MDQU2

B_MA4

A-MODT

A-MDQL4

T7

A-MDQU3

A_MA13

A_MCASB

J9 L1 L9

A-MDQU1

B-MA4

AR1213

A-MDQL3

A-MDQU2

22

A-MCASB

VSS_1 VSS_2 VSS_3

D7 C3

D8

A_MA7

A_MRASB

F1 H2 H9

NC_6

DQL7

A-MA7

22

A-MDQL2

C9 D2 E9

A9 DQSU

J8 M1

A_MA4

AR1220

NC_4 DQSL

DQSU

A-MA4

A-MRASB

A-MDQL1

A8 C1

A-MDQU0

22

A-MA2

N9 R1 R9

A-MDQU1

22

A-MRESETB

A-MDQL0

J1 NC_1 NC_2

C7 B7

B-MA5

A_MA11

VDDQ_7 VDDQ_8 VDDQ_9

E7

B_MA6

A_MA8

ODT RAS CAS

E1 G8

B-MA6

A-MA8

VDDQ_5

F3

A_MA5

A-MA11

VDDQ_4 VDDQ_6

NC_3

A-MA5

AR1218

VDDQ_3

CKE

RESET

A_MA6

22

CK

VDDQ_2

CS

T2

G3

K2 K8 N1

A1 VDDQ_1

L9 T7

D9 G7

BA1

CK

L1

A-MA6

AR1221

VDD_8

L2

H7

DQU2 DQU3

VDD_7 VDD_9

B1 VSSQ_1

D7 C3 C8

NC_5 BA0

D2 E9

DQL6 DQL7

A-MDQL6

VDD_3 VDD_4 VDD_5 VDD_6

DQSL

VSS_3

E3

H3

A_DDR3_A10

B-MA8

B_MA7

B2 VDD_1 VDD_2

A11 A12/BC

M7

A8

A9 DQSU DQSU

E7

A-MDQL4

B_DDR3_A9

B-MA7

B_MA6

A7 A8 A9

M2 N8

NC_6

C7 B7

A_DDR3_A9

G23

B-MA6

L8

A10/AP

A13

DQSL

A-MDQL3

B_DDR3_A8

H22

B_MA5

ZQ

WE

NC_4

F3

A4

J1 NC_1 NC_2 NC_3

G3

N9

A-MDMU

H1

A5 A6

R1 R9

VREFCA

VREFDQ

BA2

VDDQ_5 ODT

R3 L7 R7 N7 T3

A0 A1 A2 A3

N1

M3

VDDQ_2

WE

A-MDQL2

G7 K2 K8

A-MDML M8

A1 VDDQ_1

RESET

F8

D9

BA1

CK

T2

D7

VSSQ_2

T8 B2 VDD_1 VDD_2

A11

R8 R2

A7 A8 A9 A10/AP

CKE

A-MDQL1

P8 P2 L8

ZQ

A13

L2

DQL7 VSSQ_1

K7

P7 P3

BA2

K9

N2

A4

J7

A-MDQL0

M8

H1

VREFCA

VREFDQ

A5 A6

M7

N8

E3

IC1201-*4 K4B2G1646C N3

A1 A2 A3

M2

VSS_6

SS_2G_1333

N3 P7

A_DDR3_A8

F23

B-MA5

F9

IC1201-*3 K4B1G1646G-BCH9

P3

B_DDR3_A7

J21

B-MA3 B-MA4

B_MA4

G1

A-MDQSUB A-MDQSU

N2

D10

A_DDR3_A7

B_DDR3_A6

F24

B_MA2 B_MA3

G9

A-MDQSU

A-MDQSUB

B15

A_DDR3_A6

K20

T1

A-MDQSLB

B7

F12

B_DDR3_A5

E24

T9

A-MDQSL

C7 VSS_1

E11

A_DDR3_A5

F20

N3

B-MCKB

A-MDQSLB

G3

G13

B_DDR3_A4

D2

A-MDQSL F3

C16

B_DDR3_A3

A_DDR3_A4

E9 F1 H2

NC_3 NC_4

D11

B_DDR3_A2

A_DDR3_A3

B-MA2

DQL6 DQL7

A7

C15

A_DDR3_A2

B_MA1

C1

A9 VSS_1

E7 D3

F10

B_DDR3_A1

C9

NC_6

DQSU DQSU

AVDD_DDR0

A-MCASB R1231 A-MWEB 10K

RESET

R9

DQSL C7 B7

T2

A-MCKB

J1 NC_1

RESET

L3

K8 N1 N9 R1

A1 VDDQ_1

CK CK CKE

T2

K3

D9 G7 K2

BA1

F3 G3

A-MCK

B2

A9 A10/AP A11 A12/BC

WE

A-MODT

A14

A_DDR3_A1

G21

H1

A5 A6 A7 A8

L2 K1

F11

B_DDR3_A0

B-MA1

VREFDQ

A3

J7

J3

G9 C14

A_DDR3_A0

B-MA0 B_MA0

A4

A13 NC_5

BA2

A-MCKB

A_MBA2

M8 A0

E10

A1

M7

A-MCKE

A-MRASB

A_MBA1

IC1201-*2 K4B1G1646G-BCK0

M2

J3

A_MA14

G1

A_MBA0

N8

K1

A_MA13

D1 D8

A-MCK

C2

NC_2

B9

VSSQ_2

DQU1 DQU2 DQU3

A7 A2 B8

N8

A_MA12

T9

DQL6

H7

A-MBA0

A_MA11

M1

VSS_8

DQL2 DQL3

A_MA10

B3

VSS_2 VSS_3

E7

D7

NC_1

A_MA9

L9

NC_4 DQSL

C7

A-MA11

WE

AR1214

22

J1 L1

DQSL

L2 CS

VDDQ_6

A_MA8

J9

NC_2

F3

K7

AR1216

22

F1 H2 H9

NC_1

K9

AR1217

A-MA12

VDDQ_8 VDDQ_9

NC_3

G3

CKE

VDDQ_4

B1

D8

VDDQ_6 VDDQ_7

RAS CAS

A_MA7

C9 D2 E9

WE

A-MA10

J7

VDDQ_2

DQL6

D1

CS ODT

J3 K3 L3

P8

VDDQ_1

VSS_12

B9

C1

VDDQ_3 VDDQ_4 VDDQ_5

RESET

BA2

A9

G8

CK

T2

R7

A8

VDDQ_2

CKE

K1

DQSL

E1

K7 K9

A-MA9

A_MA6

A1 VDDQ_1

CK

L2

L7

N9 R1 R9

BA2

A-MA8

M2

NC_6

B3

VDD_7 VDD_9

BA1

M3

NC_5

VDD_7

J1 L1

A15 BA0

A_MA5

K8 N1

VDD_8

N8

J7

R3

G7 K2

VDD_4 VDD_5 VDD_6

M2

A-MA7

D9

VDD_3

A11 A13

M7

VDDQ_9

J9

VDD_1 VDD_2

M7

T8

A_MA4

B2

A9 A10/AP A12/BC

T3

C3

A1

E9

R7

R2

L8 ZQ

A7 A8

N7

A-MA6

A_MA3

H1 VREFDQ

A4 A5 A6

T8 R3 L7

C8

0.1uF

D2

R8

VREFCA

A1 A2 A3

P8 P2 R8 R2

D7

VDD_6

BA1

C9

M8 A0

P7 P3 N2

A-MA5

DQL7

VDD_9

C1

A_MA2

N3

A-MA4

P2

A13

VDD_5

0.1uF

A8

A-MA3

P8

1%

C1207

10uF

N2

A_MA1 IC1201-*1 H5TQ1G63DFR-PBC

1%

C1205

A-MA2

R1235 56

AVDD_DDR0

Hynix_1G_1600

R1236 56

R1203

P3

MAIN IC E22

F9

OS

H1

A-MVREFDQ

A_MA0

A-MA1

1%

A2

P7

56 R1237

A1

A-MA0

OS 1%

A0

VREFCA

56 R1238

N3

M8

A-MVREFCA

22

B_MBA2 B_MA3

GP4L_S7LR2 DDR_256

2011/06/03 12 LGE Internal Use Only

GP2R, LM1 Training Manual

Table of contents 1. PCB layout. 2. GP2R vs LM1 3. GP2R. (Block, Power, I2C) 4. LM1. (Block, Power, I2C) 5. LM1 SOC Power sequence. 6. Memory test. 7. Pen touch overview.

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

1. PCB Layout.

GP2R (206 x 183)

LM1 (206 x 141.5)

※ LM1 use internal EDID&HD. (LM1 is Removing the EEPROM for EDID&HD) LM1 is optimizing Power block. (LM1 is reducing DC/DC, LDO, power application)

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

2. GP2R vs GP4 LM1. Difference

GP2R 50PZ550

LM1 50PA6500

PDP Module

R3(FHD)

R4(FHD)

New module. 50R4 Initial model.

Tool

PZ Tool

PA Tool

12’ years New tool.

PCB

206x183

206x141.5

Main IC

S7R

S7LR

Jack Layout

Slim Depth

Slim Depth

Sub Assy

PZ Tool

PA Tool

GP2R 15pin, LM1 8pin

PSU

50R3 XP5 B’d

50R4 UP1 B’d

Reduce power on time.

SW

GP2R

LM1

PDP only code.

JIG

GP2R

LM1

DFT JIG.

-

.

.

Power Wafer

18P

18P

Stand by 3.5V

O

O

Stand by 3.5V .

12V_secondary

X

X

Not use 12V.

IR Wafer

15P

8P

LM1 not 3D.

USB

O

O

SIDE USB.

Memory

DDR3

DDR3

VSC

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

Changes

change PCB Size. (smaller than GP2R.) Internal sub-Micom .(PM block)

Same.

Develop new WAFER and CABLE. (12 years) Stand by 0.3W ↓

DDR3 1Gbit . 2ea LGE Internal Use Only

3. GP2R Power measure Summary Power Line

Voltage Spec [V]

Voltage [V]

+5V_ST

4.845~5.355

+5V_ST_EN

Ripple [mV]

Current [A]

5.01

86

0.009

4.845~5.355

5.00

17

0.710

+3.3V_AVDD

3.14~3.6

3.31

15

0.285

+2.5V_AVDD

2.38~2.62

2.53

20

0.200

+1.5V_DDR_IN

1.425~1.575

1.57

20

0.310

+1.26V_VDDC

1.2~1.32

1.27

30

0.770

+3.3V_ST

3.234~3.366

3.30

19

0.024

+17V

16.15~17.85

17.03

1.09A

1.420

+5V_TU

4.75~5.25

4.99

20

0.170

+5V

4.845~5.355

5.03

57

2.600

+3.3V_TU

3.15~3.46

3.26

None

26

0.320

+1.2V_TU

1.20~1.32

1.27

None

21

0.300

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

Ripple spec [Vpp]

0.5

1.5V +/-5%

0.5

None

Remark

LGE Internal Use Only

3-1. GP2R Power Block Diagram 5Vst

L603 MAX 3A

IC205 AT24C02BN RGB EDID

+5V_ST C619 100u 16V

C627 0.1u 16V

C219 0.1u 16V

C654 22u 16V

+5V_ST_EN Q600 C657 RTR030P02 C656

C655 0.01u 25V

100u 16V

0.1u 16V

IC600 AZ1085S 3.3V

C600 0.1u 16V

C607 22u 6.3V

C608 0.1u 16V

L602 2A

+3.3V_AVDD 2A/3ea

C615 0.1u 16V

S7_3.3V_AVDD

10u 2ea

0.1u 13ea

NAND Flash/HD/EEPROM

+2.5V_AVDD 2A 2A/2ea

IC604 TJ3964 C616

C623 0.1u 16V

22u 6.3V

C609 10u 16V

C611 0.1u 16V

IC602 TPA54319

10u 1ea

+1.5V_DDR_IN C637 10u 10V

C647 10u 10V

C650 0.1u 16V

2A/2ea

C610 10u 16V

C612 0.1u 16V

IC603 TPA54319

2.5V_AVDD 0.1u 4ea

10u 2ea

0.1u 32ea

10u 4ea

0.1u 10ea

DDR

S7 AVDD_DDR

+1.26V_VDDC C651 10u 10V

C652 10u 10V

C653 0.1u 16V

2A/2ea

10u 2ea

0.1u 2ea

10u 1ea

0.1u 8ea

DVDD VDDC IC203 MAX3232CDR

IC601 AP2121N 300mA

C601 0.1u 16V

+3.3V_ST C605 100u 16V

S7_MPLL

C606 0.1u 16V C552 0.1u 16V

+17V

17V

C634 4.7u 50V

C341 68u 35V

C635 4.7u 50V

C344 68u 35V

C636 0.01u 50V

C340 0.1u 50V

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

IC605 TPA54319

+5V_TU C641 10u 16V

C642 10u 16V

L610 2A

C304 22u 10V

IC503(S-FLASH) MX25L8005M2I-15G SUB ASSY

5V_TU

C307 0.1u 16V

IC303 Audio AMP STA338BWG13TR

LGE Internal Use Only

3-2. GP2R Power Block Diagram +5V

L604 3A L605 3A

+5V C621 100u 16V

C624 100u 16V

C628 0.1u 16V

L101 2A

C631 22u 16V

C103 22u 10V

IC206 AP2191

C223 100u 16V

C104 0.1u 16V

C725 10u 16V

C728 0.1u 16V

IC706 AZ1085S

C750 0.1u 16V

IC704 TPS54319

C753 22u 16V

C746 10u 10V

C747 10u 10V

L708 2A

C754 0.1u 16V

L709 2A

C748 0.1u 16V

L710 2A 0.1u 16V

+3.3V_3D

IC707 AZ1117ST C752

C751 0.1u 16V

22u 16V

L705 2A

C789 10u 16V C753 10u 16V

L706 2A L707 2A

C658 0.1u 16V

IC606 AZ1085S

C659 22u 6.3V

C660 0.1u 16V

L601 2A

C661 0.1u 16V

C126 0.1u 16V

L100 2A

1.0V

C735 0.1u 16V

R834 0Ω1/10W

C805 100p 50V C754 100p 50V

SPDIF

1.0V_LTX

13ea

C755 0.1u 16V

IC205 AT24C02 EDID USB

C222 0.1u 16V C235 0.1u 16V

L708 2A

+5V_CI_ON

0.1u 16V

0.1u 16V

7ea

0.1u 16V

7ea

0.1u 16V

3ea

33ea

IC702 MX25L4005

1.8V

3.3V_LTX 3.3V_VDD 3.3V_PLL

+3.3V_CI

C128 0.1u 16V C120 0.1u 16V C332 0.1u 50V

IC101 74LCX244

IC303 Audio AMP

+3.3V_TU L300 2A

C309 22u 10V

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

+3.3V_TU

C302 0.1u 16V

C313 0.1u 16V

IC301 AZ1117H

+1.2V_TU C325 22u 10V

C322 0.1u 16V

C300 0.1u 16V

+1.2V_TU

LGE Internal Use Only

3-3. LDO/DC-DC Start up ■ IC600 (+3.3V_AVDD/AZ1085S)

■ IC602 (+1.5V_DDR_IN/TPS54319)

Vin Vout Vin

Ve n Vo Io

■ IC604(+2.5V_AVDD/TJ3964S)

■ IC603 (+1.26V_VDDC/TPS54319)

Vin Vout

Vin

Ve n Vo Io

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

3-4. LDO/DC-DC Start up ■ IC606 (+3.3V/AZ1085S)

Vout

Vin

■ IC605 (+5V_TU/TPS54231)

Vin Ve n Vo Io

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

3-5. GP2R I2C MAP

+5V_HD MI

DDCR_CK/GPIO72 DDCR_DA/GPIO71

DDC_SCL/SDA_1~3 1 (R208,209) 2 (R233,234) 10K 3 (R256,257)

(N22) (M22)

EEPROM EEPROM 0xA0 0xA0 Ch2 Ch2

HDMI1,2,3 HDMI1,2,3 0xA0 0xA0 Ch10,12,11 Ch10,12,11 TGPIO2/I2C_CLK TGPIO3/I2C_SDA

<EEPROM-SCL>+3.3 <EEPROM-SDA> V

2.2K (R480,R482)

(R3) (T3)

HD HD EEPROM EEPROM 0xA8 0xA8 Ch2 Ch2

4.7K (R319,R326)

<SCL1>+3.3V_T <SDA1>

TUNER TUNER TDTJ-S001D TDTJ-S001D 0x10/C2 0x10/C2 Ch6 Ch6 SATURN7R SATURN7R TGPIO0/UPGAIN

+3.3V_S T

SUB_SCL SUB_SDA

(F15)I2S_IN_WS/GPIO174 (F14)I2S_IN_BCK/GPIO175

TGPIO1/DNGAIN

(U1) (U2)

2K (R360,R359)

AMP AMP STA338BWG13TR STA338BWG13TR 0x38 0x38 Ch5 Ch5

4.7K (R635,R633)

TOUCH TOUCH 0x52 0x52 Ch7 Ch7

G_EYE G_EYE 0x20 0x20 Ch7 Ch7

I2S_IN_SD/GPIO176 SPDIF_IN/GPIO177

DDCA_DA/UART0_TX

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

+3.3 V

+3.3 (F13) <MODULE_SCL/3DF_SCL> 4.7K (R780,R781) <MODULE_SDA/3DF_SDA> (G14) 3.3K (R1412,R1411) V_A VDD LG8300 MODULE LG8300 MODULE 0x74 0x74 Ch4 Ch4

DDCA_CK/UART0_RX



(B5) (A5)

0x1C 0x1C Ch4 Ch4

10K (R237,R247) EEPROM EEPROM RGB RGB 0xA0 0xA0 Ch8 Ch8

+5.0 V_ST

ISP ISP

LGE Internal Use Only

4. LM1 Power Block optimization. 1. GP2R vs LM1 Power Block.

Amp 17V

17V

5V Tuner TPS54231 2A

5.1V

1.25V Tuner LDO

3.3V 3D LDO (3A)

1.8V 3D DDR LDO

1V 3D core AOZ1073 3A

FET SW St 5V

3.3V Standby LDO(AP2121)

3.3V AVDD LDO (3A)

LDO : 7

1.25V _TU LDO (1A) 2.5V LDO (1A)

5.1V

2.5V LDO

AP2191 USB

1.24V core 1.5V DDR TPS65253(3A)

1.5V DDR AOZ1073 3A 1.26V Core AOZ1073 3A

DC/DC : 4

1.8V Tuner LDO (1A)

3.3V Multi TPS54327(3A)

AP2191 USB 3.3V Multi LDO (3A)

Amp

3.5V St.

3.3V ST AP2121

DC/DC : 2

GP2R Power Block

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LDO : 4

LM1 Power Block

LGE Internal Use Only

4-1. P_17V Spec) 850mV↓ 16mVrms 17V to 3.3V 283mVpp C620

C621

10uF

0.1uF

25V

50V

3216

2012

TPS54327 (3A, $0.14)

+3.3V

L605 2.2uH

+3.3V_CI

Spec) 165mV ↓ 4.7mVrms 46.6mVpp

L101 120 Ohm

3.5A

C629/50

C630

2A

C137

4.9x4.9

10uF

0.1uF

1608

0.1uF

16V →6.3V 3216 →1608 0.00586↓

16V

16V

1005

1005

OP-Amp for SC

1 7 V

Spec) 165mV ↓ 8.66mVrms 37.5mVpp

Buffer for CI_ADDR [0:7]

change

C667

C668

0.1uF

68uF

50V

35V

1608

8PI/6.3H

C693

C694

10uF

0.01uF

Audio AMP

+3.3V_TU

Spec) 165mV ↓ 13.5mVrms 158mVpp

L604 120 Ohm

17V to 12V TPS54231D (2A)

2A

C627

1608

3.3V to 1.8V AP1117E18G (850mW)

Spec) 90mV↓ 4.6mVrms 41.6mVpp C631

C618

10uF

10uF

0.1uF

6.3V

6.3V

16V

1608

1608

1005

Spec) 165mV↓ 23.4mVrms 166.6mVpp

25V

50V

C614

C615

3225

1005

0.1uF

10uF

16V

16V →6.3V 3216 →1608 change

C643 0.1uF C711

C712

10uF

0.1uF

16V

50V

3216

1608

LNB

50V 1608

Audio AMP

Spec) 165mV↓ 8.5mVrms 186.6mVpp

1005

Tuner

C638 C646 0.1uF 50V 1608

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

4-2. P_17V * Y17

+2.5V

+3.3V

Spec) 165mV↓ 7.8mVrms 47.5mVpp

x3 3.3V to 2.5V TJ3940S-2.5V (714mW)

120 Ohm

L613

LM1

120 Ohm

C612

2A

C1417

x6

2A

C682

C671

10uF

10uF

1608

10uF

0.1uF

1608

0.1uF

10uF

6.3V

6.3V

16V

16V

1608

1608

10V →6.3V 2012 →1608 change

1005

1005

10V →6.3V 2012 →1608 change

C605

Tuner

DVB_T2

1 7 V

* W18/9

Spec) 165mV↓ 9.7mVrms 67.5mVpp

L408/9 120 Ohm 2A

x5

X4

1608

0.1uF

10uF

16V

10V →6.3V 2012 →1608 change

1005

x3

C427

0.1uF

10uF

16V

10V →6.3V 2012 →1608 0.00636↓

1005

Nand Flash

x2

C554

0.1uF

10uF

16V

10V →6.3V 2012 →1608 change

1005

LM1

* L7

change

3.3V to 1.25V AP1117EG-13 (???mW)

C625 10uF 6.3V 1608

HD

Spec) 165mV↓ 8.5mVrms 45mVpp

+1.25V_TU

C552

Tuner

NVR

0.1uF

C684

C685

16V

0.1uF

10uF

1005

16V

6.3V

1005

1608

NOT_HNIM

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

4-3. P_5V

Spec) 250mV↓ 7mVrms 70mVpp

L600 120 Ohm 5A

C608

C610

2012

10uF

0.1uF

10V →16V 2012 →3216 0.0005↓ change

5 V

+5V

USB OCD

16V 1005 C219

SPDIF

0.1uF 16V 1005

+5V_CI_ON

Spec) 250mV↓ 31mVrms 135.4mVpp

L100 MOFET Switch

120 Ohm 2A

C104

C100

C101

1608

0.1uF

22uF

0.1uF

16V

10V →16V 3216 →3225 0.017↓

1005

PCMCI

16V 1005

change

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

4-4. P_5V * M14

+1.24V_VDDC

+5V L606

L405

???mVrms

120 Ohm

120 Ohm

Spec) 55mV↓ 9.4mVrms 48.3mVpp C1413 ???mVrms

5A

C653/4

C683/57

2A

x2

2012

10uF

22uF

1608

0.1uF

10uF

25V

16V

16V

3225

3225

1005

10V →6.3V 2012 →1608 change

5V to 1.1V TPS65253RH D (adjustable) $0.25

x3

x3

0.1uF

10uF

16V

10V →6.3V 2012 →1608 change

1005

5 V

* R15

LM1 Spec) 55mV↓ 17.7mVrms 70mVpp

* M17

+1.5V_DDR_IN

Spec) 55mV↓ 15.9mVrms 90mVpp

L412 120 Ohm C651/56

C467

2A

x4

x4

22uF

1000pF 50V

1608

10uF

0.1uF

1uF

16V

16V

10V

3225

1005

10V →6.3V 2012 →1608 change

1005

1005

VCC_1.5V_DDR

LM1 MIU0/1

C468

* IC501 / G7

Spec) 55mV↓ 19.69mVrms 120.8mVpp

L500 500 Ohm 3A

C544

C545

x2

x2

???

10uF

0.1uF

1000pF

0.1uF

10V →6.3V 2012 →1608

16V

50V

16V

1005

1005

1005

DDR1/2

change

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

4-5. STBY Spec) 250mV↓ 23mVrms 150mVpp

C600

C601

10uF 10V →16V 2012 →3216

5V to 3.3V AP2121N-3.3 (0.3A)

+3.3V_ST

C604

C228

0.1uF

1uF

0.1uF

16V

6.3V

16V

1005

1005

1005

RS232C

0.0005↓ change

L406 120 Ohm

S T B Y

2A

C469

1608

0.1uF

LM1

16V 1005

C556

Serial Flash

0.1uF 16V 1005

C547

SUB Ass’y

0.1uF 16V 1005

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

4-6. GP4 LM1 I2C MAP

EAX64337201_0 +3.3V_TU

I2C_SCKM1/GPIO75 I2C_SDAM1/GPIO76

AE6 AD6

TU_SCL TU_SDA

IC400

R3082.2K

R309 2.2K

TU300 TDSS-G201D +3.3V

GPIO49 GPIO50

AB5 AB3

AMP_SCL AMP_SDA

R624 2K

R623 2K

IC300 STA368BWG

+3.3V_AVDD

I2S_IN_WS/GPIO149 SPDIF_IN/GPIO152

D9 D7

P_SCL P_SDA

R468 3.3K

R466 3.3K

SCL_3.3V_MOD P500 SDA_3.3V_MOD LVDS

+3.3V_ST

I2S_IN_SD/GPIO151 I2S_IN_BCK/GPIO150

D8 C8

SUB_SCL SUB_SDA

R539 4.7K

R538 4.7K

P501 KEY/IR PIN8 +3.3V_AVDD

I2C_SCKM2/DDCR_CK/GPIO72 I2C_SDAM2/DDCR_DA/GPIO71

P23 P24

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

I2C_SCL I2C_SDA

R469 2.2K

R468 2.2K

IC503 EEPROM IC502 HD (OTP) LGE Internal Use Only

5. GP4 LM1 SOC Power Sequence Procedure ▶Hot Point

288ms / [Spec] before all pwr input raise SOC_RESET +3.3V_AVDD +1.10V_VDDC

Multi_PWR 0ms

+1.5V_DDR_IN

SOC_RESET Threshold

+3.3V_AVDD

+1.10V_VDDC

+1.5V_DDR_IN

◈ SOC_RESET timing and Power sequence are ok.

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

5. GP4 LM1 SOC Power Sequence Procedure ◈ Solution

█ Value of Capacitor and resister. ① Cap Æ 22uF. 0CK226DC67A 22uF 6.3V

$0.0117

② Resister Æ 100㏀.

+3.3V_AVDD

1

Threshold SOC_RESET

2

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

6. Memory margin test. (DDR) STEP1. Setting like below. (Red box)

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

STEP2. Call “direct MIU Auto BIST” function from Menu.

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6. Memory margin test. (DDR) STEP3. Setting like below and push “Start DQS”. (Red box)

STEP4. below picture is test result. Red box is timing margin.

※Normal operating board has timing margin 7~9. If timing margin under 7 ,it’s some problem DDR or Main MIU.

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

7. Pen touch overview. (Installation_Pentouch Program.)

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

7. Pen touch overview. (Installation_Pentouch Program.)

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

7-1. Pen touch overview. (Check the installation status.) 1

Currently installed programs Check the LG Pentouch Multi-touch Driver or Pentouch TV

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

2

Check USB Dongle Driver in Device Manager -LG Pentouch Multi-touch Driver(MultiTouch) -LG Pentouch Multi-touch Driver(BUS) -LG Pentouch Multi-touch Driver(Dongle) the Dongle Driver should be displayed when connected USB Dongle

LGE Internal Use Only

7-2. Pen touch overview. (Pairing between Touch Pen and Dongle)

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

7-3. Pen touch overview. (Pairing between Touch Pen and Dongle)

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

7-4. Pen touch overview. (Using the Pentouch Function) ■ Image shown may differ from your monitor. You need the following items to use the Pentouch functions: 1 Enter the Pentouch mode on your monitor. - Press TOUCH button on the remote control or MENU to access the main menus. Then choose Pentouch function. 2 Select the correct computer input connection to enter the Pentouch mode.

3 Use the touch pen or the mouse to start the Pentouch program. Pressing the /Home button on the touch pen works in the same way as right-clicking the mouse.

■ Viewing the Screen Settings I mage shown may differ from your monitor. If you press the OK button on the remote control, the screen shown below appears to indicate that the screen settings have been updated successfully.

① The text "Pentouch" should be displayed to indicate that the Pentouch mode is activated. If not, restart the Pentouch mode. ② "1365x768 " should be displayed to indicate that the resolution has been set successfully. If not, set the monitor resolution again.(See p.38)

Copyright © 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

7-5. Pen touch overview. (PDP Pen Touch Concept)

Principle 2. The position data processed Pentouch TV Application looks like PC mouse. Step 1. USB Dongle receive the position data. Step 2. USB Dongle Driver parsing the positon Step 3. Pentouch TV application drawing and click function. Step 4. The result was displayed PDP TV through HDMI or RGB cable.

Principle 1. The Pen using PDP Cell’s light energy Step 1. The pen detect the PDP Cell’s light Step 2. The pen convert detected light to voltage Step 3. The pen calculate X,Y position Step 4. The pen transfer the X,Y data through RF

Pen The photo sensor in the pen detect the light

RF Wireless communication (2.4GHz)

USB Dongle It can use Multi-Touch function by 2 pens.

Plasma Display

Pentouch TV Application - It was developed by LG. - It can be using internet for web surfing , Flash Game etc.

The HDMI or RGB signal is PC’s output that configuration set by clone mode.

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LGE Internal Use Only