Comparison Study Of Finfets - Soi Versus Bulk 2dt71

Comparison study of FinFETs: SOI vs. Bulk Performance, Manufacturing Variability and Cost David Fried, IBM Thomas Hoffmann, IMEC Bich-Yen Nguyen, SOITEC Sri Samavedam, Freescale

Horacio Mendez, SOI Industry Consortium

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SOI industry Consortium proprietary

Goal of the Study To compare the performance, process variability, and cost of potential FinFET process flows based on SOI and bulk silicon wafers

The study will show Both SOI and bulk FinFETs should be able to achieve comparable performance. Bulk FinFETs will require a more complex doping implementation. Bulk FinFETs will have difficult variability control. The estimated cost differential of processed wafers using the Bulk and SOI substrates is within the accuracy of our projections.

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Discussion Outline •3 Cases (Proposed Flows): - SOI FinFET - Bulk FinFET – Junction Isolation - Bulk FinFET – Material Isolation

•Performance Analysis: - Transistor performance - Parasitic element comparison - Leakage comparison

•Variability Analysis •Cost/Complexity Analysis 3

Discussion Outline •3 Cases (Proposed Flows): - SOI FinFET - Bulk FinFET – Junction Isolation - Bulk FinFET – Material Isolation

•Performance Analysis: - Transistor performance - Parasitic element comparison - Leakage comparison

•Variability Analysis •Cost/Complexity Analysis 4

Case 1:SOI FinFET flow The fin trench etch simply stops on the wafer’s buried oxide layer

PR

PR

HM SOI

BOX

BOX

BOX

Si-sub

Si-sub

Si-sub

PR

Because of the buried oxide layer, adjacent fins are fully isolated from each other and no additional isolation steps are needed

HM

Fin

gate

oxide BOX oxide Si-substrate SOI-FinFET

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Fin

HM SOI

In the fully-depleted, undopedchannel devices being considered for this node, only source and drain implants, followed by gate fabrication, are needed to complete the device

Junction Isolated Bulk FinFET flow PR

oxide HM

HM Si-sub

HM

HM Si-sub

HM

HM

Si-sub

Fin

HM

HM

Si-sub

HM

Si-sub

Si-sub

The oxide deposition must fill a deep, high aspect ratio trench Timed etch

Fin

gate

Oxide provides insulation between adjacent fins, the transistors are still connected underneath the oxide. A high dose junction implant at the base of the fin completes the isolation

oxide Si-substrate

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Bulk-FinFET (“junction isolated”)

Material Isolated Bulk FinFET flow

HM

Si-sub

oxide

PR

PR

Si-sub

HM

HM

HM

Si-sub

HM

Si-sub

HM

HM

Si-sub

Fin

gate

oxide

HM

HM

Si-sub

HM

HM

HM

Si-sub

HM

Si-sub

Si-sub

Fin

• Oxide is allowed to grow from the oxide trench isolation across the bottom of the fin.

Si-substrate • Because of its complexity, we do not expect the material isolation approach

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Bulk-FinFET (“material isolated”)

will be viable for manufacturing and have not analyzed it as closely.

Discussion Outline •3 Cases (Proposed Flows): - SOI FinFET - Bulk FinFET – Junction Isolation - Bulk FinFET – Material Isolation

•Performance Analysis: - Transistor performance - Parasitic element comparison - Leakage comparison

•Variability Analysis •Cost/Complexity Analysis 8

DC performance benchmarking Parvais et al., VLSI-TSA, 2009

SOI FinFET

250 1.E-04 1.E-05 1.E-06

25nm

200

Ioff_s [A/um]

1.E-07

BOX

26nm 65nm

DIBL [mV/V]

67nm

150

1.E-08 1.E-09 1.E-10 1.E-11 1.E-12 1.E-13 1.E-14 0

100 200 300 400 500 600 700

100

Idsat [uA/um]

50

Bulk FF SOI FF

0 Bulk FinFET

10

100 Lg [nm]

At matched (Wfin, Hfin) equivalent performance & SCE for SOI-FF and Bulk-FF 9

1000

Leakage comparison

• One possible issue in forming a Ground Plane for Bulk-FF isolation : - Finite doping gradient Fin body gets partially doped from bottom-up

• Therefore, difficult to dope sufficiently (~15e18) under the Fin, wo/ doping significantly the Fin body mobility loss from impurity scattering, increases RDF

Manoj et al., IEEE TED. 2008

• Junction isolated Bulk-FF can potentially match SOI in of sub-VT leakage control, but doping optimization can be complex 10

Parasitics capacitance & AC performance Manoj et al., IEEE TED. 2008

Highly doped Source/Drain

GP

Cj

• Junction isolated Bulk-FF has intrinsically more parasitic capacitance than SOI (due to junction capacitance) - Cf. work from Manoj et al., IEEE TED’08

• However, if Hfin > 40-50nm, the impact of the junction capacitance penalty of Bulk-FF over SOI-FF (in of RO delay) can be kept below ~5-6% 11

Discussion Outline •3 Cases (Proposed Flows): - SOI FinFET - Bulk FinFET – Junction Isolation - Bulk FinFET – Material Isolation

•Performance Analysis: - Parasitic element comparison - Leakage comparison

•Variability Analysis •Cost/Complexity Analysis 12

SOI FinFET Variability PR

Fin

PR

gate

Fin

HM SOI

HM SOI

BOX

BOX

BOX

Si-sub

Si-sub

Si-sub

BOX Si-substrate

SOI-FinFET

Nominal

3-sigma Tolerance (current)

3-sigma Tolerance (future)

nm

70

2

1

Hardmask dep

nm

10

1

0.5

10% cross-wafer 3sigma

Fin Etch

nm

70

4.2

2.1

5% cross wafer + 1% overetch

Corner rounding

nm

2

0.1

0.05

4.8

2.4

Root sum-square of all sources of variability

0.5

In 32nm technology, active area CD variability is 15nm across iso-dense patterns, multiple pitchs and RIE overetch from variability in vertical layers. For FinFETs, most of the CD variability is expected to come from the overetch to for thickness variability in Fin definition since the pitch will be fixed. Assumption is that 20% of the vertical variability will translate to CD (Fin width) variabiliy.

Sources of Variability

Unit

SOI Layer

Total fin height variability (nm)

Total fin width variability (nm)

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1.0

5% 3sigma SOI thickness variability with future improvements in high volume manufacturing

Bulk FinFET (Junction isolated) Variability PR

PR HM

HM

HM

Fin Si-sub

Si-sub

Si-sub

oxide HM

HM

HM

gate

Fin

HM

oxide Si-substrate

Si-sub

Si-sub

Nominal

3-sigma Tolerance (current)

3-sigma Tolerance (future)

nm

8

0.4

0.2

5% 3sigma variation for oxide

HM nitride

nm

70

7

3.5

10% 3sigma variation for deposited nitride

Trench etch

nm

170

8.5

4.25

5% 3sigma from trench etch based on 32nm data

Oxide recess

nm

100

5

2.5

Oxide dry/wet etch with no etch stop. 100nm oxide etchback for 70nm fin height assumed.

Pad oxide

nm

2

0.1

0.05

Well anneal

nm

0

3

1.5

3sigma variability in junction depth from angled implants

12.5

6.2

Root sum-square of all sources of variability

1.2

Assumption is that 20% of the vertical variability will translate to CD (Fin width) variability. See previous slide for more details on fin width variability.

Sources of Variability

Unit

HM oxide

Total fin height variability (nm)

Total fin width variability (nm)

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Si-sub

2.5

Variability Comparison of SOI FinFETs vs Bulk FinFETs

SOI-based FinFET

FEOL

Junction-isolated bulk FinFET

Litho steps

Process steps

Litho steps

Process steps

7

56

9

91

process

3-sigma variability in Fin Height 3-sigma variability in Fin width

current future current future

SOI FF (nm) 4.8 2.4 1 0.5

Bulk-junction isolation FF (nm) 12.5 6.2 2.5 1.2

% variability relative to SOI 160 158 150 140

• Fin height and fin width variability in bulk FinFETs (both material isolated and junction isolated versions) is expected to be ~140-170% higher compared to SOI FinFETs

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Discussion Outline •3 Cases (Proposed Flows): - SOI FinFET - Bulk FinFET – Junction Isolation - Bulk FinFET – Material Isolation

•Performance Analysis: - Parasitic element comparison - Leakage comparison (Junction Isolation)

•Variability Analysis: - Effective Width Variation

•Cost/Complexity Analysis 16

Cost Analysis for FinFET on SOI vs. Bulk FinFET on SOI Litho

Process

Steps

steps

Substrate FEOL Process

FinFET on Bulk

Cost

Litho

Process

Steps

steps

$500 7

56

$561

9

91

Cost

Delta Cost

$120

$380

$805

-$244

Total Cost difference

$136

Assumption: 1.

All circuitries can be converted to the undoped channel FinFET architecture for both SOI and Bulk.

2.

SOI substrate cost of $500 will be available in 2012 with high volume manufacturing

3.

Generic FEOL process flows for FinFET on SOI and Bulk . Cost only included 1 gate dielectric thickness, 1 Vt for N- and PMOS to metal 1. No capacitors, resistors, eDRAM, ESD, I/O,…. Additional processes for fabrication of multi Vt, Dual or triple gate dielectric thickness, more circuitries and metal interconnect layers will add more process costs for both approaches.

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% Cost Difference (Bulk (Bulk-SOI)

Bulk vs SOI FinFET Cost Analysis 8 6.1%

6

4.9% 4.1%

3.5%

4

3.1%

2 0 -2

-3.4%

-2.7%

-2.3%

-4

-5.4%

-1.7% -4.8%

-6.3%

-6 -8

-1.9%

-7.6% % Process cost (Bulk-SOI)

-9.5%

% Substrate cost (Bulk-SOI)

-10

% Process+substrate cost (Bulk-SOI)

-12 3000

4000

5000

6000

7000

8000

9000

Total Wafer Cost ($)

• The SOI finFET wafer cost increment over bulk depends on the final wafer cost. 18

Summary • This study evaluated the performance, variability and cost differences between FinFETs fabricated with Bulk and SOI substrates. 3 process flows were compared: • SOI FinFET • Bulk FinFET – Material Isolation • Bulk FinFET – Junction Isolation

• Similar DC & AC performance for SOI-FF & Bulk-FF are observed • Junction isolated Bulk-FF has intrinsically more parasitic capacitance than SOI but the impact of the junction capacitance penalty can be kept below ~5-6%

• Doping appears more complex for Bulk-FF • Fin height & Fin width variability appear to be significantly larger for Bulk-FinFET this lead important wafer manufacturing and product control challenges • Our study indicates that at high-Volume the cost difference of SOI-FinFET over BulkFinFET is less than 4%

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