Cmos Analog Circuit Design Holberg 144p2o

;

Diffusion

Figure l.l-6 Side view of CMOS integrated cil'l!uir.

I

I

I

I

1

1

, '

•

i

I

1

•

.

2.2 The pn junction

{a)

29

(b)

Figure 2.1-7 (a) Polycide structure and (b) salicide structure.

Silicide technology was born out of the need to reduce interconnect resistivity. For with it, a low-resistance silicide such as TISi 2, WSi2, TaSi 2, or several other candidate silicides is placed on top of polysilicon so that the overall polysilicon resistance is greatly reduced without compromising the other salient benefits of using polysilicon as a transistor gate (wellknown work-function and polysilicon-Si interface properties). Salicide technology (self-aligned. silicide)* goes one step further by providing lowresistance source/drain connections as well as low-resistance polysilicon. Examples of silicide

and salicide transistor cross sections are illustrated in Fig. 2.1-7 [23}. For analog designs, it is important to have available polysilicon and diffusion resistors that are not salicided, so a good mixed-signal process should provide a salicide block. There are many other details associated with CMOS processes that have not yet been described here. Furthermore, there are different variations on the basic CMOS process just described. Some of these provide multiple levels of polysilicon as well as additional layers of metal interconnect. Others provide good capacitors using either two layers of polysilicon, two layers of metal (MOM capacitors), or polysilicon on top of a heavily implanted (on the same order as a source or drain) diffusion. Still other processes start with an n- substrate and implant p-wells (rather than n-wells in a p- substrate). The latest processes also use shallow trench isolation (STI) instead of LOCOS to eliminate the problem of oxide encroachment into the width of a transistor. Newer processes also employ chemical mechanical polishing (CMP} to achieve maximum surface planarity.

2.2 THE

PM JUNCTION The pnjunction plays an important role in all semiconductor devices. The objective of this section is to develop the concepts of the pnjunction that will be useful to us later in our study. These include the depletion-region width. the depletion capacitance. reverse-bias or breakdown voltage, and the diode equation. Further information can be found in the references [24,25]. "The tenns silicide and salicide are often interchanged. Moreover, polycide is used to refer to polysilioon witb silicide.

30

CMOS TECHNOLOGY

Figure 2.2-1 (a) shows the physical model of a pn junction. In this model it is assumed that the impurity concentration changes abruptly from Nv donors in then-type semiconductor to NA acceptors \n the p-type semiconductor. This situation is caUed a step junction and is illustrated in Fig. 2.2-l(b). The distance xis measured to the right from the metallurgical junction at x = 0. When two different types of semiconductor materials are formed in this manner, the free carriers in each type move across the junction by the principle of diffusion. As these free carriers cross the junction, they leave behind fixed atoms that have a charge opposite to the carrier. For example, as the electrons near the junction of the n-type material diffuse across the junction they leave fixed donor atoms of opposite charge ( +) near the junction of the n-type material. This is represented in Fig. 2.2-1 (c) by the rectangle with a height of qND- Similarly, the holes that diffuse across the junction from the p-type material to the n-type material leave behind fixed acceptor atoms that are negatively charged. The electrons and holes that diffuse across the junction quickly recombine with the free majority carriers across the junction. As positive and negative fixed charges are uncovered near the junction by the diffusion of the free carriers, an electric field develops that creates an opposing carrier movemenL When the current due to the free C
(t}

' {a)

io .___ ___;>11;:...._ _-o+"o

(b)

--o---------....1

"l

(d)

Potential (V)

(e)

~lion cflargc co!IC"nlnlli<m (m1'3)

Figure 2.2-1 pn Junction: (a) pbysiclll structure, (b) impurity concentralion, (c) depletion charge concentration, (d) electric field, and (e) electrostatic potential.

2.2

The pn Junction

31

Thus, (2.2-2) where q is the charge of an electron (1.60 X 10- 19 C). The electric field distribution in the depletion region can be calculated using the point fonn of Gauss's law: dE(x)

qN

dx

Bsi

--=-

(2.2-3)

By integrating either side of the junction. the maximum electric field that occurs at the junction, Eo. can be found. This is illustrated in Fig. 2.2-l(d). Therefore, the expression for E0 is {2.2-4) where es; is the dielectric constant of silicon and is 11.7eo (Bois 8.85 X 10-•~ F/cm). The voltage drop across the depletion region is shown in Fig. 2.2-l(e). The voltage is found by integrating the negative electric field, resulting in

fllo- vo

=

-E0 (x,.- Xp)

(2.2-5)

2

where v0 is an applied external voltage and t/Jo is called the barrier potential and is given 85

fllo

= kT In (N"No) = q

nf

V, In (N"No)

n;

(2.2-6)

Here, k is Boltzmann's constant (1.38 X 10- 23 J/K) and n; is the intrinsic concentration of silicon, which is 1.45 X 101%m 3 at 300 K. At room temperature, tbe value of V, is 25.9 mV. It is important to note that the notation for kT!q is V, rather than the conventional VT· The reason for this is to avoid confusion with Vr. which will be used to designate the threshold voltage of the MOS transistor (see Section 2.3). Although the barrier voltage exists with v0 = 0, it is not available externally at the terminals of the diode. When metal leads are attached to the ends of the diode a metal-semiconductor junction is formed. The barrier potentials of the metal-semiconductor s are exactly equal to f/1 0 so that the open circuit voltage of the diode is zero. Equations (2.2-2), {2.2-4), and (2.2-5) can be solved simultaneously to find the width of the depletion region in the n-type and p-type semiconductors. These widths are found 85

x = [ 2Bs;(tPo - l'o)N~o] 112 "

qNo(NA

+ N0 )

(2.2-7)

and x = -[2Bs;(f/lo- Vo)No] P

qN~o(N,..

+ N0 )

112

(2.2-8)

J2

CMOS TECHNOLOGY

The width of the depletion region, x8 , is found from Eqs. (2.2-1 ), (2.2-7) and (2.2-8) and is

(2.2-9)

It can be seen from Eq. (2.2-9) that the depletion width for the pn junction of Fig. 2.2·1 is proportional to lhe square root of the difference between the barrier potential and the externally applied voltage. It can also be shown thatxd is approllimately equal to x,.or Xp for N,.. >> N0 or N0 >> N,... respectively. Consequently. the depletion region will extend further into a lightly doped semiconductor than it will into a heavily doped semiconductor. It is also of interest to characterize the depletion charge Q1, which is equal to the magnitude of lhe fixed charge on either side of the junction. The depletion charge can be expressed from the above relationships as

(2.2-10)

where A is the cross-sectional area of the pn junction. The magnitude of the electric field at the junction £ 0 can be found from Eqs. (2.2-4) and (2.2-7) or (2.2-8). This quantity is expressed as

(2.2-11)

Equations (2.2-9), (2.2-1 0), and (2.2-1 1) are key relationships in understanding the pn junction. The depletion region of a pn junction forms a capacitance called the depletion-layer capacitance. It results from the dipole formed by uncovered fixed charges near the junction and will vary with tbe applied voltage. The depletion-layer capacitance C) can be found from Bq. (2.2-10) using the following definition of capacitance:

(2.2-12)

C.10 is the depletion-layer capacitance when v0 == 0 and m is called a grading coefficient. The coefficient m is t for the case of Fig. 2.2-1, which is called a step junction. If the junction is fabricated using diffusion techniques described in Section 2.1, Fig. 2.2-1 (b) will become more like the profile of Fig. 2.2-2. lt can be shown for this case that m is!. The range of values of the grading coefficient will fall between ~ and Figure 2.2-3 shows a plot of the depletion-layer capacitance for a pn junction. It is seen that when v0 is positive and approaches t/lo, the depletion-layer capacitance approaches infinity. At this value of voltage, the assumptions made in deriving the above equations are no longer valid. In particular, the assumption that the depletion region is free of charged carriers is not true. Consequently, the actual curve bends over and c1 decreases as v0 approaches tf>o [26].

!.

2.2 lhe pn Junction

33

Figure 2.2-Z Impurity concenlrlllion profile for diffused pnjunction.

Figure 2:.2-3 Depletion capacitance as a function of externally applied junction voltage.

CHARACTERISTICS OF A PN JUNCTION Find x,. x.,. x"' ~O> Cj(lo and c1 for an applied voltage of -4 V for a pn diode with a step junction, N,.. = 5 X I0 1'fcm3, N0 = llfll/cm3, and an area of 10 IJ..m by 10 IJ..m.

lfdMU.i.i At room temperature, Eq. (2.2-6) gives the barrier potential as 0.917 V. Equations (2.2-7) and (2.2-8} givexft ae 0 andxP = 1.128 fJ.m. Thus, the depletion width is approximately xP or 1.128 fJ.m. Using these values in Eq. (2.2-12) we find that CJO is 20.3 fF and at a voltage of -4 v. qis 9.18 fF. The voltage breakdown of a reverse-biased (v0 < 0) pnjunction is determined by the maximum electric field£,.,. that can exist across the depletion region. For silicon, this maximum electric field is approximately 3 X l~ Y/cm. If we assume that lvol > !Jio, then substituting E....,. into Eq. (2.2-11) allows us to express the maximum reverse-bias voltage or breakdown voltage (BV) as

BV:!; Ss;(N,.. + No)lfmu. 2qNAND

(2.2-13}

Substituting the values of Example 2.2-1 in Eq. (2.2-13) and using a value of 3 X 1~ V/cm for Emall gives a breakdown voltage of 58.2 V. However, as the reverse-bias voltage starts to approach this value, the reverse current in the pn junction starts to increase. This increase is due to two conduction mechanisms that can take place in a reverse-biased junction between two heavily doped semiconductors. The first conduction mechanism is called avalanche multiplication and is caused by the high electric fields present in the pn junction; the second is called Zener breakdown. Zener breakdown is a direct disruptio)\ of valence bonds in high electric fields. However, the Zener mechanism does not require the presence of an energetic

34

CMOS TECHNOLOGY

ionizing carrier. Tbe current in most breakdown diodes will be a combination of these twt1· conduction mechanisms. H iRis the reverse current in the pn junction and vR is the reverse-bias voltage across lhe pn junction, then the actual reverse current iliA can be expressed as

(2.2-14) M is the avalanche multiplication factor and n is an exponent that adjusts the sharpness of the '"knee" of the curve shown in Fig. 2.2-4. Typically, n varies between 3 and 6. If both sides of the pn junction are heavily doped, the breakdown will take place by tunneling, leading to the Zener breakdown, which generally occurs at voltages less than 6 V, Zener diodes can be fabricated where an n"'" diffusion overlaps with a p+ diffusion. Note that the Zener diode is com· patible with the basic CMOS process although one tenninal of the Zener must be either on the lowest power supply, Vss• or the highest power supply, Vvo· The diode voltage-current relationship can be derived by examining the minority-carrier concentrations in the pn junction. Figure 2.2-5 shows the minority-carrier concentration for a forward-bia.'ied pn junction. The majority-carrier concentrations are much larger and are not shown on this figure. The forward bias causes minority carriers to move across the junction. where they recombine with majority carriers on the opposite side. The excess of minoritycarrier concentration on each side of the junction is shown by the shaded regions. We note that this excess concentration starts at a maximum value at x = 0 (x' = 0} and decreases to the equi· librium value asx (x') becQmes large. The value of the ex.cess concentratioll atx = Q, designated aspn (0), or .t' = 0, designated as np(O), is expressed in of the forward-bias voltage v0 as Pn(O)

=p.oexp (~)

(2.2-15)

np(O)

== n,.o exp ( ~)

(2.2-16)

and

where P.o and 11p0 ate the equilibrium concentrations of the minority carriers in the n-type and p-type semiconductors, respectively. We note that these value.~ are essentially equal to the intrinsic concentration squared divided by the donor or acceptor impurity atom concentration, as shown on Fig. 2.2-5. As v0 is increased. the excess minority concentrations are increased. Figure 2.2-4

Rcverse-bia~ voltag~urrenl

characteris-

tics of the pn junction. illustrating voltage breakdown.

0

1

2.2

The pn Junction

35

n,t_x')

np(O) =~~p~~ex{f)

X

X

Figure 2.2·5 Impurity concentration profile for diffused pn junction.

If v0 is zero, there is no excess minority concentration. If vv is negative (reverse-biased) the

minority-carrier concentration is depleted below its equilibrium value. The current that fl.ows in the pn junction is proportional to the slope of the excess minoritycarrier concentration at x = 0 (x' = 0). 'Ibis relationship is given by the diffusion equation expressed below for holes in the n-type material. (2.2-17) where Dp is the diffusion constant of holes in n-type semiconductor. The excess holes in the n-type material can be defined as

(2.2-18) The decrease of excess minority carriers away from the junction is exponential and can be expressed as

p~(x) = p~(O) exp ( ~:) = [piO) -

p 110] exp (

~:)

(2.2-19)

where L, is the diffusion length for holes in ann-type semiconductor. Substituting Eq. (2.2-15) into Eq. (2.2-19) gives (2.2-20) The current density due to the excess-bole concentration in then-type semiconductor is found

by substituting Eq. (2.2-20) into Eq. (2.2-17), resulting in Jp(O)

= qD~:no [exp (~)-I]

(2.2-21)

l6

CMOS TECHNOLOGY

Similarly, for the excess electrons in the p-type semiconductor we have (2.2-22)

Assuming negligible recombination in the depletion region leads to an expression for the total current iJensity of the pn junction, given as J(O) =

Jp(O) + Jn(O) = q [D~..o + D~":] [exp (~) -

(2.2-2:3)

1]

Multiplying Eq. (2.2-23) by the pnjunction area A gives the total current as in== qA [

D~..o + D~: }[exp (;,)- 1] = 1,[exp (~)-

I]

(2.2-24)

Is is a constant called the saturation current. Equation (2.2-24) is the familiar voltage-current relationship that characterizes the pn junction diode.

CALCULATION OF THE SATURATION CURRENT

From Eq. (2.2-24), the saturation current is defined as

2.l03/cm3; RpO is calculated from nFINA to get 4.205 X l 0 fcm • Changing the units of area from p.m2 to cm2 results in a saturation current magnitude of 1.346 X 10- u A or 1.346 fA.

pml is calculated from nr!No to 4

gel

3

This section has developed the depletion-region width, depletion capacitance, breakdown voltage, and the voltage-current characteristics of the pn junction. These concepts will be very important in detennining the characteristic8 and performance of MOS active and ive components.

2.3

THE MOS TRANSISTOR The structure of an n-channel and p-channel MOS transistor using an n·well technology is shown in Fig. 2.3-1. The p-channel device is formed with two heavily doped p + regions diffused into a lightly doped n- material called the well. The two p+ regions are called drain

2.3

The MOS Transistor

37

JT' subslr.l>te

Figure 2.3-1 Physical structure of an n-channel and p-channe1transistor in an o-well technology.

:.

and source and are separated by a distance L (referred to as the device length). At the surface between the drain and source lies a gate electrode that is separated from the silicon by a thin dielectric material (silicon dioxide). Similarly, the a-channel transistor is formed by two heavily doped o+ regions within a lightly doped p- substrate. It, too, has a gate on the surface between the drain and source separated from dle silicon by a thin dielectric material

(silicon dioxide). Essentially, both types of transistors are four-tenninal devices as shown in Fig. 1.2-2(c,d). The B terminal is the bulk, or substrate, which contains the drain and source diffusions. For an n-well process, the p-bulk connection is common throughout the integrated circuit and is connected to Vss (the most negative supply). Mulliple n-wells can be tilbricated on a single circuit, and they can be connected to different potentials in various ways depending on the application. Figure 2.3-2 shows an n-channel transistor with all four terminals connected to ground. At equilibrium, the p- substrate and the n + source and drain form a pn junction. Therefore, a depletion region exists between the n+ source and drain and the p- substrate. Since the source and drain are separated by back-to-back pn junctions, the resistance between the source and drain is very high (> 1012 fl). The gate and the substrate of the MOS transistor form the parallel plates of a capacitor with the Si02 as the dielectric. This capacitance divided by the area

p· substrak:

Figure 2.3-2 Cross section of an n-channel transistor with all tenninals grounded.

J8

CMOS TECHNOLOGY of the gate is designated as Cu~· * When a positive potential is applied to the gate with respect to the source a depletion region is fonned under the gate resulting from boles being pushed away from the silicon-silicon dioxide interface. The depletion region consists of fixed ions that have a negative charge. Using one-dimensional analysis, the charge density, p, of the depletion region is given by

P"" q(-N,)

(2.3-1)

Applying the point form of Gauss's law, the electric field resulting from this charge is E(x)

P

=

-dx

Je

:=

f

-qN,., -qN, --dx = --x + C SsJ

(2.3-2)

BsJ

where Cis the constant of integration. The constant. C, is determined by evaluating E(x) at the edges of the depletion region (x = 0 at the Si-Si02 interface; x = xd at the boundary of the depletion region in the bulk). E(O) =

-qN.., esi

Eo = - - 0 + C = C

(2.3-3)

(2.3-4)

(2.3-5) This gives an expression for E{x): E(x)

qN, = es;

(xd - x)

(2.3-6)

Applying the relationship between potential and electric field yields (2.3-7) Integrating both sides of Eq. (2.3-7) with appropriate limits of integration gives

"'J'dt/> = - fz"qN, Bst (xd "'·

x) dx =

(2.3-8)

0

"The symbol C normally bas units of farads; however, in the field of MOS devices it often has units of farads per unit area (e.g., F/m2).

2.3

qNAx~ -- = 2ssl

The MOS Transistor

tPs - tPF

39

(2.3-9)

where rpp is the equilibrium electrostatic potential (Fermi potential) in the semiconductor, rPs is the surface potential of lbe semiconductor, and xd is the thickness of lbe depletion region. For a p-type semiconductor, rPF is given as (2.3-10)

and for ann-type semiconductor tPF is given as (2.3-11)

Equation (2.3-9) can be solved for x4 assuming that lt/J, -

rp~ ~

0 to get (2.3-12)

The immobile charge due to acceptor ions that have been stripped of lbeir mobile holes is

given by Q=-qN,.,h

(2.3-13)

Substituting Eq. (2.3-12) into Eq. (2.3-13} gives (2.3-14)

When the gate voltage reaches a value called the threshold voltage, designated as Vr. the substrate underneath the gate becomes invened; that is, it changes from a p-type to an n-type semiconductor. Consequently, ann-type channel exists between the source and drain that allows carriers to ftow. In order to achieve this inversion, lbe surface potential must increase from its original negative value (rp, = 1/Jp), to zero (t/1., = 0). and then to a positive value (1/J, = -rpp). The value of gate-source voltage necessary to -cause this change in surface potential is defined as the threshold voltage, Vr. This condition is known as strong inversion. Then-channel transistor in this condition is illustrated in Fig. 2.3-3. With the substrate at ground potential, the charge stored in the depletion region between the channel under the gate and the substrate is given by Eq. (2.3-14), where q,, has been replaced by -rp,to for the fact that vas= VrThis charge QbO is wrinen as (2.3-15)

If a reverse-bias voltage v8 s is applied across the pn junction, Bq. (2.3-15) becomes (2.3-16)

-40

CMOS TECHNOLOGY

FOX

FOX

------/{ lnvct1ed chat1nel p- substrate

-: :-dy:

!-- WyJ---!y !•

y=.O

~

y=L

y.+-dy

Figure 2.3-3 Cross section of llll n-channel transistor with small Y~:~s lllld VG$

>

V7'

An expression for the threshold voltage can be developed by breaking it down into several components. First, !:he tenn* tbus must be included to represent the difference in the work functions between the gate material and bulk silicon in the channel region. The tenn tPMs is given by tPMs

= tPF (substrate) -

q,, (gate)

(2.3-17)

-zq,,..-

where ,P,(metal) = 0.6 V. Second, a gate voltage of [ (Q~o/C.,,)) is required to change the surface potential and offset the depletion-layer charge Qb· Lastly, !:here is always an undesired positive charge Q., present in the interface between the oxide and the bulk silicon, This charge is due to impurities and imperfections at the interface and must be compensated by a gate voltage of -(b,JC0 ,. Thus, the thre.<>hold voltage for the MOS transistor can be expressed as

Vr = 4»Ms

+

(

Qh) + (-Q - -. . ) C.,,

-2(/IF--

C.,.

(2.3-18)

The threshold voltage can be rewritten as

(2.3-19) where V 7ll

=. ..MS-

2~F

-

Qw

Q,. -C

OX

""

C -

{2.3-20}

•Historically. this term has been referred to as the metal·fO·silicon work: function. We will continue the tradition even when the gate terminal is something other than melal (e.g., polysilicon).

2.3 The MOS Transistor

41

TABLE 2.3-1 Signs for the Quantities in the Threshold Voltage Equation Parameter

n-Channel (p-Type Substrate)

p-Channel (n· Type Substrate)

~t.iS

Metal a+ Si gate p+ Si gate

..,

+

Q..

+

+

+

a60o a. Vsa

+

'(

+

+ +

and the body factor, body-effect coefficient, or bulk-threshold parameter -y is defined as (2.3·21) The signs of the above analysis can become very confusing. Table 2.3·1 attempts to clarify any confusion that might arise [25].

CALCULATION OF THE THRESHOLD VOLTAGE Find the thre.~hold voltage and body factor -y for an n-channel transistor with an n + silicon gate if t0 , = 200 A, NA = 3 X 10 16 em - 3 , gate doping, N0 = 4 X 10 19 em - 3 , and if the number of positively charged ions at the oxide-silicon interface per area is 10 10 em - 2 •

&taMII.J.M From Bq. (2.3-10), rPF(subslrate} is given as 16

3 X 10 ) tPp(substrate) = -0.0259 In ( = -0.377 V 1.45 X 1010 The equilibrium electrostatic potential for the n + polysilicon gate is found from Eq. (2.3-11) as

.p,(gate)

= 0.0259ln (

19

4 X 10 ) = 0.563 V 1.45 X 10 10

Equation (2.3-17) gives .PMs as rflp(substrate) - q,,(gate) = -0.940 V

<&2

CMOS TECHNOLOGY The oxide capacitance is given as C....

= e.,.It , = 3.9 X 8.854 X to-•• 0 200 X 10-8

= 1.727 X

I0-1 R'J,em2

The fixed charge in the depletion region, QIJOo is given by Eq. (2.3-15) as

QIJO = - (2 X 1.6 X = -8.66 x

10-l!l

X 11.7 X 8.854 X 10- 14 X 2 X 0.377 X 3 X 10 1 ~ 112

to-• C/cm3

Dividing QbO by Co.. gives -0.501 V. Finally, Q./Co. is given as

Q.. 10 -= C.._.

10 X ]

1

60 X 10- ' ' 1.727 X 107

9.3 X 10-3 V

Substituting these values into Eq. (2.3-18) gives

Vrn = - 0.940

+ 0.754 + 0.501 - 9.3 X 10 -l = 0.306 V

The body factoris found from Eq. (2.3-21) a.s

'Y

=

(2

X

1.6 X l0-19 X 11.7 X 8.851

X

10-14 X 3 X 10 16) 112

1.727 X 107

=0.577 V 112

The above example shows how the value of impurity concentrations can influence the threshold voltage. In fact, the threshold voltage can be set to any value by proper choice of the variables in Eq. (2.3-18). Standard practice is to implant the proper type of ions into the substrate in the channel region to adjust the threshold voltage to the desired value. 1f the opposite impuritie.~ are implanted in the channel region of the substrate, the threshold for an n-cbannelrransistor can be made negative. This type of transistor is called a depletion transistor and can bave current ftow between the drain and source for zero values of the gate-source voltage. When the channel is formed between the drain and source as illustrated in Fig. 2.3-3, a drain current i 0 can flow if a voltage vDs exists across the cbannel. The dependence of this drain current on the tenninal voltages of the MOS transistor can be developed by considering the characteristics of an incremental length of the channel designated as dy in Pig. 2.3-3. It is assumed tlult the width of the MOS transistor {into the page) is Wand that vm is small. The charge per ,,mit area in the channel, Q1(y), can be expressed as

..

(2.3-22) The resiStance in the channel per unit of length dy can be written as

(2.3-23}

2.4

ive Components

43

where ~'• is the average mobility of the electrons in the channel. The voltage drop, referenced to the source, along the channel in the y direction is (2.3-24)

or (2.3-25) Integrating along the channel from y

= 0 toy = L gives

Iil>dy = fWJ.InQ,(y) dv(y) = Iwl'.ca..[Vas- v(y)- Vr] dv(y) L

"w

"'•

0

0

(2.3-26)

0

Performing the integration results in the desired expression for iv as

i0

zw[

v(yil""' (vas- Vr)v(y)- - -_b 2

= I'•C

=

(2.3-27)

J.l.c.,. w [(Vas L

)

Vr Vm -

2~vs]

This equation is sometimes called the Sah equation [27] and has been used by Shichman and Hodges [28] as a model for computer simulation. Equation (2.3-27) is valid only when

(2.3-28)

·-

and for values of L greater than the minimum L. The factor J.I.C01 is often defined as the device-transconductance parameter, given as

K' =

n

.-n

C = 01

P.,Ela.

tao

(2.3-29)

Equation (2.3-28) will be examined in more detail in the next chapter, concerning the modeling of MOS transistors. The operation of the p-channel transistor is essentially the same as that of the n-channel transistor, except that all voltage and current polarities are reversed.

2.4 PRSSIYE COMPONENTS This section examines the ive components that are compatible with fabrication steps used to build the MOS device. These ive components include the capacitor and the resistor.

14

CMOS TECHNOLOGY

Capacitors A good capacitor is often required when deg anategrated circuits. They are used as compensation capacitors in amplifier designs, gain-determining components in charge amplifiers, bandwidth-determining components in gm/C filters, charge storage devices in switched-capacitor filters and digital-to-analog converters, and other places as well. The desired characteristics for capacitors used in these applications are: • Good matching accuracy • Low voltage coefficient • High ratio of desired capacitance to parasitic capacitance • High capacitance per unit area • Low temperature dependence Analog CMOS processe.~ differentiate themselves from purely digital ones by providing capacitors that meet the above criteria_ For such analog processes, there are basically three types of capacitors made available. One type of capacitor, called aMOS capacitor, is fonned using one of the available interconnect layers (metal or polysilicon} on top of crystalline silicon separated by a dielectric (silicon dioxide layer). Figure 2.4-l(a) shows an example of this capacitor using polysilicon as the top conducting plate. In order to achieve a low-voltagecoefficient capacitor, the bottom plate must be heavily doped diffusion (similar to that of the source and drain). As the process was described in Section 2.3, such heavily doped diffusion is normally not available underneath polysilicon because the source/drain implant step occurs after polysilicon is deposited and defined. To solve this problem, an extra implant step must

(a)

(b)

(c)

Figure 2.4-1 MOS capacitors. (a} PolysilicoD-Oxide channel (b) Polysilicon-oxide-polysilicon. (c) Accumulation MOS capacitor.

2.4

ive Components

45

be included prior to deposition of the poJysilicon layer. The mask-defined implanted region becomes the bottom plate of the capacitor. The capacitance achieved using this technique is inversely proportional to gate oxide thickness. Typical values for a 0.& jJ.IIl process are given in Thble 2.4-1. This capacitor achieves a high capacitance per unit area and good matching performance but has a significant voltage-dependent parasitic capacitance to the substrate. The second type of capacitor available in analog-tailored processes is that fonned by providing an additional poly silicon layer on top of gate polysilicon (separated by a dielectric), An example of a double polysilicon capacitor is liJustrated in Fig. 2.4-l(b). The dielectric is formed by a thin silicon dioxide layer. which can only be produced by using several steps beyond the usual single polysilicon process. This capacitor does an excellent job of meeting the criteria set forth above. In fact. it is the best of all possible choices for high-perfonnance capacitors. Typical values for a 0.8 J.Lm process are given in Table 2.4- t. A third type of capacitor is lllustrated in Fig. 2.4-l(c). This capacitor is constructed by putting an n-well underneath an n-channel transistor. It is similar to the capacitor in Fig. 2.4l(a) except that its bottom plate (the n-weU) has a much higher resistivity. Because of this fact, it is not used in circuits where a low voltage coefficient is important. It is often used, however, when one terminal of the capacitor is connected to ground (or '-':~5). It offers a very high capacitance per unit area, it can be matched well, and it is available in all CMOS processes because no unique steps or masks are required. Quite often, the processing performance required by the digital component of a mixed· signal integrated circuit necessitates the use of a process targeted for digital applications. Such processes do not provide tailored capacitors for analog applications. Therefore, when a capacitor is needed, it must be derived from two or more of the interconnect layers. Figure 2.4-2 illustrates symbolically various schemes for making capacitors in one-, two-, and three-layer metal digital processes. In Fig. 2.4-2(a) capacitors are constructed verticalJy using the interlayer oxide as the capacitor dielectric. The four-layer example achieves the highest ratio of desired capacitance to parasitic capacitance, whereas the two-layer capacitor achieves the lowest As processes migrate toward finer Hnewidths and higher speed performance. the oxide between metals increa.<;es while the allowed space between metals decreases. For such processes, same-layer horizontal capacitors can be more efficient than different-layer vertical capacitors. This is due to the fact that the allowed space between two M 1 lines, for example, is less than the vertical space between M t and M2 (see Fig. 2.1-6). An example of a same-layer TABLE 2.4-1 Approximate Performance Summary of ive Components in a 0.8 JJ.m CMOS Process Component Type MOS capacitor Poly/poly capacitor M 1-Poly capacitor M2-M 1 capacitor M3-M2 capacitor p + Diffused resistor n+ Diffu!ied te$l~tor Poly resistor n-WeU resistor

Range of ValUe$

Matching Accuracy

Temperature Coefficient

Voltage Coefficient

2.2-2.7 IF/j1.1112

0.05% 0.05%

SOppmi"C SOppmi"C

50ppm/V 50ppm1V

1500 ppmi"C 1500 ppmi"C 1500 ppmi"C 8000ppmi"C

200ppm/V 200ppmN JOOppmN IOkppmN

0.8-1.0 1Fip.m2 0.021-0.0251F/...m1 0.021-0.025 IF/ ...m2 0.021--{1.025 fFI1J.m2 80-150fll0

50-800/0 20-400/0 1-2 k!l/0

1.5%

1.5% 1.5% 0.4% 0.4% 0.4%

-46

CMOS TECHNOlOGY

J!I~ M2

1(1!}

F1gure 2.4-2 Various ways to implement capacitors using available interconnect layers illustrated with a side view. Ml, M2. and M3 represent the first. secolld. and third metal layers, respectively. (a) Venical parallel plate structures. {b) Horizon!S.l parallel plate structures.

(a)

(b)

horizontal capacitor is il111strated in Fig. 2.4-2(b). Compared to polysilicon-oxide-polysilcon capacitors, these capacitors typically suffer from lower per-unit-area capacitance and lower ratio of desired capacitance to parasitic capacitance. Matching accuracy of capacitors implemented Like those in Fig 2.4-2 is on the order of 1-2% and voltage coefficient is low. Typical values for vertical capacitors in a 0.8 f.IJll process are given in Table 2.4-1. The voltage coefficient of integrated capacitors generally falls within the range of 0 to -200 ppm/V depending on the structure of the capacitor and, if applicable, the doping concentration of the capacitor plates f29). The temperature coefficient of integrated capacitors is found to be in the range of 20---50 ppmi"C. When considering lhe ratio of two capacitors on the same substrate, note that the variations on the absolute value of the capacitor due to temperature tend to canceL Therefore, temperature variations have little effect on the matching accuracy of capacitors. When capacitors are switched to different voltages, as in the case of sampled--data circuits, the voltage coefficient can have a deleterious effect if it is not kept to a minimum. The parasitic capacitors associated with the capaciton; of Figs. 2.4- t and 2.4-2 can give rise to a significant so11rce of error in analog sampled-data circuits. The capacitor plate with the smallest parasitic associated with it is referred to as the top plate. It is not necessarily physically the top plate although quite often it is. In contrast, the bottom plate is the plate having the larger parasitic capacitance associated with it. Schematically, the top plate is rep-

2.4

Top ~~~te

:-----1 J_ 1

ive Components

47

Figure 1.4.3 A model for the integrated capacitors showing top and bouom plate parasilics.

Cdoli.m

parasttlC .........

:'

•I

v

---· .. -t

' ...!.-

Bottom plare

'i' parasilic o

v

resented by the flat plate in the capacitor symbol while the curved plate represents the bottom plate. Por the capacitors iiiustrated in Fig. 2.4-1 the parasitic capacitor associated with the top plate of the capacitor itself is due primarily to interconnect lines leading to the capacitor and the bottom plate parasitic capacitance is primarily due to the capacitance between the bottom plate and the substrate. The capacitors available in a digital process shown in Fig. 2.4-2 have parasitics that are not so easily generalized. The parasitics are very dependent on the layout of the device (layout is discussed in Section 2.6). Figure 2.4-3 shows a general capacitor with its top and bottom plate parasitics. These para* sitic capacitances depend on the capacitor size, layout, and technology and are unavoidable.

Resistors The other ive component compatible with MOS technology is the resistor. Even though we shall use circuits consisting of primarily MOS active devices and capacitors, some applications, such as digital-to-analog conversion, use the resistor. Resistors compatible with the MOS technology of this section include diffused, polysilicon, and n-well (or p-well) resistors. Though not as common, metal can be used as a resistor as well. A diffused resistor is fanned using source/drain diffusion and. is shown in Fig. 2.4-4(a). The sheet resistance of such resistors in a nonsalicided process is usually in the range of 50-150 fliD (ohms per square are explained in Section 2.6). Por a salicide process, these The fact that the source/drain diffusion is needed as a resistors are in the range of 5-15 conductor in integrated circuits conflicts with its use as a resistor. Clearly, the goal of a salicide process is to achieve "conductor-like" performance from source/drain diffusion. In these processes, a saUcide block can be used to mask the silicide film, thus allowing for a highresistance source/drain diffusion where desired. The diffused resistor is found to have a voltage coefficient of resistance in the I00-500 ppm/V range. The parasitic capacitance to ground is also voltage dependent in this type of resistor. A poly silicon resistor is shown in Fig. 2.4-4(b). This resistor is surrounded by thick oxide and has a sheet resistance in the range of 30-200 fll[], depending on doping levels. For a polysilicide process, the effective resistance of the polysilicon is about 10 n/0. Ann-well resistor shown in Fig. 2.44(c) is made up of a strip of n-wells ed at both ends with n + source/drain diffusion. This type of resistor has a resistance of 1-10 k!l/0 and a high value for its voltage coefficient. In cases where accuracy is not required, such as pull-up resistors or protection resistors, this structure is very useful. Other types of resistors are possible- if the process is altered. The three categories above represent those most commonly applied with standard MOS technology. Table 2.~1 summarizes the characteristics of the ive components hitherto discussed.

ruo.

48

CMOS TECHNOLOGY Metal

(b)

(a)

Mcbll

FOX p· ..bslntc (c)

Figun! 2.4-4 Resistors: (a) diffused, (b) polysilicon, and (c} n-weU.

2.S

OTHER CONSIOERRTIONS OF CMOS TECHNOLOGY In the previous two sections, the active and ive components of the basic CMOS process have been presented. In this section we wish to consider some other components that are also available from the basic CMOS prO<:ess but that are not used as eJttensively as the previous components. We will further consider some of the limitations of CMOS technology, including latch-up, temperature, and noise. Thi~ information will become useful later, when the performance of CMOS circuits is characterized. So far we have seen that it is possible to make resistors, capacitors. and pn diodes that are compatible with the basic single-well CMOS fabrication process illustrated in Fig. 2.3-1. It is also possible to implement a bipolar junction transistor (BIT) that is compatible with this process, even though the collector terminal is constrained to Vv0 (or Vss>· Figure 2.5-1 shows bow the BIT is implemented for ann-well process. The emitter is the source or drain diffusion of a p-channel device, the base is the n-well (with a base width of w8 ), and the p- substrate is the collector. Because the pn junction between the n-well and the p- substrate must be reverse biased, the collector must always be connected to the most negative power-supply voltage, Vss· The BIT will still find many useful applications even though the collector is constrained. The BJT illustrated in Fig. 2.5- I is often called a substrate Bfr. The sub&trate BJT functions like the BJT fabricated in a prO<:ess designed for BJTs. The only difference is that the collector is constrained and the base width is not well controlled. resulting in a wide variation of current gains. Figure 2.5-2 shows the minority-carrier concentrations in the BIT. Normally, the base-emitter (BE) pn junction is forward biased and the collector-base ( CB) pn junction is reverse biased. The forward-biased BE junction causes free holes to be injected into the ba..'le region. If the base width w8 is small, most of these holes reach the CB junction and are swept

2.5

Other Considerations of CMOS Technology

49

Figure 2.5-l Substrate BJT available

from a bulk CMOS process.

-CoD""""' (y oubaraU!)

into the collector by the reverse-bias vol1age. lf the minority-carrier concentrations are much less than the majority-carrier concentrations, then the collector current can be found by solving for the current in the base region. In of current densities, the collector current density is

Jc = -lp\t,_ =

-qD dpn(x) P dx

= qD P

pn(O) Ws

(2.5-1)

From Eq. (2.2-16) we can write (2.5-2) Combining Eqs. (2.5-1} and {2.5-2) and multiplying by the area of the BE junction A gives the collector current as

(Ves) = I,exp (VEB) -

• tc= Ale= qADp11n0 exp ws

PpE.

V,

V1

---r--""

.t=O

x=ws

JC

Figure 2.5-l Minority-cwrier concentrations for a bipolar junction tran· si.slor. ·

(2.5-3)

50

CMOS TECHNOLOGY

where /, is defined as (2.5-4)

As the holes travel through the base, a small fraction will recombine with electrons, which are tbe majority carriers in the ba.<~e. As this occurs, an equal number of electrons must enter the base from the external base circuit in order to maintain electrical neutrality in the base region. Also, there will be injection of the electrons from the base to the emitter due to the forward-biased BE junction. This injection is much smaller than the hole injection from the emitter because the emitter is more heavily doped than the base. The injection of electrons into the emitter and the recombination of electrons with holes in the base both constitute the external base current i8 that flows out of the base. The ratio of collector current to base current, idi& is defined as (3F or the common-emitter current gain. Thus, the base current is expressed as

. ic

I,

'a = fJF = (3F exp

(vEB) V,

(2.5-5)

The emitter current can be found from the base current and the collector current because the sum of all three currents must equal zero. Although {!JF has been assumed constant it varies with i0 having a maximum for moderate currents and falling off from this value for large or small currents. In addition to the substrate BIT, it is also possible to have a lateral BIT. Figure 2.3-1 can be used to show how the lateral BIT can be implemented. The emitter could be then+ source of the n-channel device, the base the p- substrate, and the collector then-well. Although the base is constrained to the substrate potential of the chip. the emitter and collector can have arbitrary voltages. Unfortunately, the lateral BIT is not very useful because of the large base width. In fact, the lateral BIT is considered more as a parasitic transistor. However, this lateral BJT becomes important in the problem oflatch-up of CMOS circuits, which is discussed next [30). lAtch-up in integrated circuits may be defined as a high current state accompanied by a collapsing or low-voltage condition. Upon application of a radiation transient or certain electrical excitations. the latched or high current state can be triggered. Latch-up can be initiated by at least three regenerative mechanisms: (l} the four-layer, silicon-controlled rectifier (SCR), regenerative switching action; (2) secondary breakdown; and (3) sustaining voltage breakdown. Because of the multiple p and n diffusions present in CMOS, they are susceptible to SCR latch-up. Figure 2.5-3(a) shows across section of Fig. 2.3-1 and bow the PNPN SCR is formed. The schematic equivalent of Fig. 2.5-3(a} is given in Fig. 2.5-3(b). Here the SCR action is clearly iUustrated. The resistor RN is the n-well resistance from the base of the vertical PNP (Q2) to V00• The resistor R,. is the substrate resistance from the base of the lateral NPN (Q2) to Vss· Regeneration occurs when three conditions are satisfied. The first condition is that the loop gain must exceed unity. This condition is stated as (2.5-6) where f3NPN and f!JPNP are the common-emitter, current-gain ratios of Q2 and QI. respectively. The second condition is that both of the base-emitter junctions must become forward biased.

,

2.5


Sl

...

(a)

(b)

Figure 2.5·3 (a) Parasitic lateral NPN and vertical PNP bipolar transistor in CMOS integrated circuits. (b) Equivalent circuit of the SCR formed from the parasitic bipolar transistors.

The third condition is that the circuits connected to the emitter must be capable of sinking and sourcing a current greater than the holding current of the PNPN device. To prevent latch-up, several standard precautions are taken. One approach is to keep the source/drain of the n-channel c;levice as far away from tb~ n-well as PQssible. This reduces the value of 13NPN and helps to prevent latch-up. Unfortunately, this is very costly in of area. A second approach is to reduce the values of RN- and Rr. Smaller resistor values are helpful because more current must flow through them in order to forward bias the ba~e--emitter regions of QI and Q2. These resistances can be reduced by surrounding the p-channel devices with an n + guard ring connected to Vol> and by surrounding n-channel transistors with p .. guard rings tied to Vss a" shown in Pig. 2.5-4. Latch-up can also be prevented by keeping the potential of the source/drain of the p-channel device {A in Fig. 2.5-3(b}] from being higher than VDD or the potential of the source/drain of then-channel device [Bin Fig. 2.5-3(b)] from going below Vss. By careful design and layout, latch-up can be avoided in most cases. In the design of various circuit.,, particularly those that have high currents, one must use care to avoid circuit conditions that will initiate latch-up. p-.ehannel tnuJ&.iator

n+ guard bars

\

p· substrate Figure :Z.S-4 Preventing latch-up using guard bars iD an n-welltechnology.

52

CMOS TECHNOLOGY

Another important consideration of CMOS technology is the electrostatic discharge protection of the gate.q of transistors that are externally accessible. To prevent accidental destruction of the gate oxide, a resistance and two reverse-biased pn junction diodes are employed to form an input protection circuit. One of the diodes is connected with the n side to the highest circuit potential (Van) and the p side to the gate to be protected. The other diode is connected with the n side to the gate to be protected and the p side to the lowest circuit potential (V55). This is illustrated in Fig. 2.5-5. For an n-well process, the first diode is usually made by a p• diffusion into then-well. The second diode is made by ann+ diffusion into the substrate. The resistor is connected between the e)ltemal and the junction between the diodes and the gate to be protected. If a large voltag-e is applied to the input, one of the diodes will break down depending on the polarity of the voltage. lf the resistor is large enough, it will limit the breakdown current so that the diode is not destroyed. This circuit should be used whenever the gates of a transistor (or transistors) are taken to external circuits. The temperature dependence of MOS components is an imponant performance characteristic in analog circuit design. The temperature behavior of ive components is usually expressed in of a fractional temperature coefficient TCF defined as . 1 dX TCr=-·X dT

(2.5-7)

where X can be the resistance or capacitance of the ive component. Generally, the fractional temperature coefficient is multiplied by 10~ and expressed in units of parts per million per "C or ppmi"C. The fractional temperature coefficient of various CMOS ive components has been given in Table 2.~ l. The temperature dependence of the MOS device can be found from the expression for drain current given in Eq. (2.3-27). The primary temperature-dependent parameters are the mobility p. and the threshold voltage Vr. The temperature dependence of the carrier mobility p. is given as [3 1I (2.5-8) The temperature dependence of the threshold voltage can be approximated by the following expression [32]: (2.5-9)

To internal garcs n+- substrate diode (b)

Figure 2.5-5 Electrostatic: discharge protection circuitry. (a} Electrical equivalent circuit {b) lmplemenllltiun in CMOS technology.

2.S


53

where a is. approximately 2.3 mV/°C. This expression is valid over the range of 200-400 K, with a depending on the substrate doping level and the implant dose Used during fabrication. These expressions for the temperature dependence of mobllity and threshold voltage will be used later to determine the temper.1ture performance of MOS circuits and are valid only for limited ranges of temperature variation about room temperature. Other modifications are necessary for extreme temperature ranges. The temperature dependence of the pn junction is also important in this study. For example. the pn-junction diode can be used to create a reference voltage whose temperature stability will depend on the temper4ture characteristics of the pn-junction diode. We shall consider the reverse-biased pn-junction diode first. Equation (2.2-24) shows that, when vD < 0, the diode cuiTent is given as -i0

95/1

DpPttO

Dnnpa]

qAD

nF

:~.

(-Voo)

=qA [ - - + - - es---=KT exp - Lp Ln L N V,

(2.5-10)

where it has been assumed that one of the in the brackets is dominant and that L and N coiTespond to the diffusion length and impurity concentration of the dominant term. Also Tis the absolute temperature in kelvin units and V00 is the bandgap voltage of silicon at 300 K (1.205 V). Differentiating Eq. (2.5-10) with respect to Tresults in 3

3

( -VGO) dl, = --exp 3KT qKT V00 exp (-Vm) 31, I, Voo -dT -- + - - "' - + - T V, KT 2 V, T T V

(2.5-11)

1

The TCF for the reverse diode current can be expressed as 1 dl,

3

(,dT

T

l Vuo TV,

--=-+--

(2.5-12)

The reverse diode cUITent i~> ~>een to double approximately every 5 °C increase as illustrated in the following eltample. CALCULATION OF THE REVERSE DIODE CURRENT TEMPERATURE DEPENDENCE AND TC, Assume that the temperature is 300 K (room temperature) and calclJiate the reverse diode current change and the TCI'l for a 5 °C increase.

Solution The TCFcan be calculated from Eq. (2.5-12) as TCF

= 0.01 + 0.155 = 0.165

Since the TCF is change per unit of temperature the reverse cUITent will increase by a factor of 1.165 for every kelvin (or QC) change in temperature. Multiplying by 1.165 five times gives an increase of approximately 2. This implies that the reverse saturation cUITent will approximately double for every 5 °C temperature increase. Experimentally, the reverse current doubles for every 8 °C increase in temperature because the reverse cUITent is in part leak· age CUITent.

54

CMOS TECHNOLOGY

The forward-biased pn-junction diode current is given by (2.5-13) Differentiating this expre....~ion with respect to temperarure and assuming that the diode voltage is a constant (v0 = V0 ) gives

din

lo dl,

1 Vo .

-=-·---·-lo tiT I. tfi' T V,

(2.5-14)

The fractional temperature coefficient for io results from Eq. (2.5-14) as (2.5-15) If V0 is assumed to be 0.6 V, then the fractional temperature coefficient is equal to 0.01 + (0.155- 0.077) = 0.0879. It can be seen that the forward diode current will double for ap-

proximately a 10 °C increase in temperature. The above analysis for the forward-biased pn-junction diode assumed that the diode voltage v0 was held constant. If the forward current is held constant (i0 = /0 ), then the fractional temperature coefficient of the forward diode voltage can be found. from Eq. (2.5-13) we can solve for v0 to get

v0

~ V,ln (;,)

(2.5-16)

Differentiating Eq. (2.5-16) with respect to temperature gives

dvo = v

0 _

tfr

T

V. I

(.!.I. dl,) = tiT

V1> _

T

3V, _ ~.GO T

T

= _ (Voo- Vo) _ 3V, T

T

(2.5-17)

Assuming that v0 = V0 = 0.6 V, the temperature dependence of the forward diode voltage at room temperature is approximately -2.3 mV/°C. Another limitation of CMOS components is noise. Noise is a phenomenon caused by small fluctuations of the analog signal within the components themselves. Noise results from the fact that eleclrical charge is not continuous but the re.<;ult of quantized behavior and is associated with the fundamental processes in a semiconductor component. In essence, noise acts like a random variable and is often treated as one. Our objective is to introduce the basic concepts concerning noise in CMOS Gomponeqts. More detail can be found in several excellent references [24.33]. Several sources of noise are important in CMOS components. Shot noise is associated with the de current flow across a pnjunction.lt typically has the form (2.5-18)

2.6

Figure 2.5-6

Noise power

Integrated Circuit Layout

IQnoit~e

55

spectrum.

spectral density

log(j)

where~~ is the mean-square value of the noise current, q is the charge of an electron, 10 is the average de current of the pnjunction, and &/is the bandwidth in hertz. Noise-current spectral density can be found by dividing i~ by af, The noise-current spectral density is denoted as il,.J~f. Another source of noise, called thermal noise, is due to random thermal motion of the electron and is independent of the de current flowing in the component It generally has the form

e! =

4kTR llf

(2.5-19)

where k is Boltzmann's constant and R is the resistor or equivalent resistor in which the thermal noise is occurring. An important source of noise for MOS components is the flicker noise or the 1/f noise. This noise is associated with carrier traps in semiconductors, which capture and release carriers in a random manner. The time constants associated with this process give rise to a noise signal with energy concentrated at low frequency. The typical form of the 1/fnoise is given as (2.5-20) where K1 is a constant, a is a constant (0.5-2), and b is a constant (-1). The noise-current spectral density for typical 1/f noise is shown in Fig. 2.5-6. Other sources of noise exist, such as burst noise and avalanche noise, but are not important in CMOS components and are not discussed here.

2.G INTEGRATED CIRCUIT LAYOUT The final subject in this chapter concerns the geometrical issues involved in the design of integrated circuits. A unique aspect of integrated-circuit design is that it requires understanding of the circuit beyond the schematic. A circuit defined and functioning properly at the schematic level can fail if it is not correctly designed physically. Physical design. in the context of integrated circuits, is referred to as layout. As a designer works through the process of deg a circuit, he/she must consider . all implications that the physical layout might have on a circuit's operation. Effects due to matching of components or parasitic components must be kept in mind. If, for example, two

56

CMOS TECHNOLOGY

transistors are intended to exhibit identical performance, their layout must be identical. A wide-bandwidth amplifier design will not function properly if parasitic capacitances at critical nodes are not minimized through careful layout. To appreciate these finer issues dealing with physical design, it is important to first develop a basic understanding of integrated-circuit lay· out and the rules that govern it. As described in Section 2.1, an integrated circuit is made up of multiple layers, each de-fined by a photomask using a photolithographic process. Each photoma.~k is built from a computer database, which describes it geometrically. This database is derived from the physical layout drawn by a mask designer or by computer (at present, most analog layout is still performed manually). The layout consists of topological descriptions of all electrical components that will ultimately be fabricated on the integrated circuit. The most common components that have been discussed thus far are transistors, resistors, and capacitors.

Matching Concepts As will be seen in later chapters, matching the performance of two or more components is very imponant to overall circuit operation. Since matching is dependent on layout topology, it is appropriate to discuss it here. The rule for making two compooents electrically equivalent is simply to draw them as identical units. This is the unit-marching principle. To say that two components are identical means that both they and their surroundings must be identical. This concept can be explained in nonelectrical tenns. Consider the two square components, A and B, illustrated in Fig. 2.6-1 (a). In this example, these objects could be pieces of metal that are desired after deposition and etching. They have identical shape in area and perimeter as drawn. However, the surroundings seen by A and B are different due to the presence of object C. The presence of object C nearer to object B may cause that object to change in some way different than A. The solution to this is to force the surroundings of both geometries A and B to be the same. This can never be achieved perfectly! However, matching performance can normally be improved by at least making the immediate surroundings identical, as illustrated in Fig. 2.6-l(b). This general principle will be applied repeatedly to components of various types. When it is desired to match components of · different sizes, optimal matching is achieved when both geometries are made from integer numbers of units with all units being designed applying the unit-matching principle.

Figure 2.6-1 (a) TI!uslration of how matching of A and B is disturbed by the presence of C. (b) lmprovtd matching achieved by matching sunoundings of A and B.

2.6


57

When multiple units are being matched using the unit-matching principle, another issue can arise. Suppose that there is some gradient that causes objects to grow smaller along some path. a.~ illustrated in Fig. 2.6-2(a). By design, component A composed of units A 1 and A2 should be twice the size of unit component B. However, due to the gradient, component A is less than twice the size of component B. If the gn1dient is linear, this situation can be resolved by applying the principle of common-centroid layout. As illustrated in Fig. 2.6-2(b), component B is placed in the center (the centroid) between the units A1 and A2• Now, any linear gradient will cause A 1 to change by an amount equal and opposite to A 2 such that their average value remains constant with respect to B. This is easily shown analytically in the following way. If the linear gradient is described as

y=mx+b

(2.6-1)

then for Fig. 2.6-2(a) we have (2.6-2) (2.6-3)

B=mx3+b

A,

+ A2 B

m(x 1 + xJ + 2b IIIX]

+b

(2.6-4)

(2.6-5)

This ratio cannot be equal to two because (2.6-6)

I

I

I

(a)

At

A2

B

(b)

At

B

A2

.' 'Y

_.-j

-----

-"I

Figu n 2.6-2 Components placed in the presence of a gradient. without common-centroid layout and (b) with commoncentroid layout. (a)

58

CMOS TECHNOlOGY However, for the case illustrated in Fig. 2.6-2(b) it is easy to show that (2.6-7) if x1

- ~ and .t2 - .t3 are ~ual. The matching principle~ described thus far should be applied to capacitors when it is desired to match them. In addition, there are other rules that should be applied when dealing with capacitors. When laying out a capacit-or, the capacitor's value should be determined by only one plate to reduce its variability. Consider the dual-plate capacitors shown in Fig. 2.6-3. In this figure, the electric field lines are illustrated to indicate that the capacitance between the plates is due to both an area field and fringe field. In Fig. 2.6-3(a) the total capacitance between the two plates will vary if the edges of the top plate indicated by points A and A' move, or if the edges of the bottom plate indicated by points B and B' move. On the other hand, the value of the capacitor illustrated in Fig. 2.6-3(b) is sensitive only to the edge variations of the top plate. Even if the top plate shifts to the left or to the right by a small amount, the capacitance changes very Jinle. The capacitor in Fig. 2.6-3(a) is sensitive to movement of both plate.~ and thus will have greater variability due to process variations than the capacitor in Fig. 2.6-3(b). The field lines illustrated in Fig. 2.6-3 are helpful to appreciate the fact that the total capacitance between two plates is due to an area component (the classic parallel plate capacitor) and a perimeter component (the fringe capacitance). With this in mind. consider a case where it is desired to ratio two capacitors, C 1 and C1, by a precise amount (e.g., 2:1 ratio). Let C1 be defined as

(2.6-8) and C2 be defined as (2.6-9) where

CxA is the area capacitance (parallel plate capacitance) CXP is the peripheral capacitance (the fringe capacitance) The ratio of C 2 to C 1 can be expressed as

c2

c,

=

A

«t~- ~

iI'

8 (a}

C2A + c2P C2A[1 + c2p1c2AJ ctA + ciP = c,A 1 + c.p~c.A

.

A'

A

(w 8'

(2.6-10)

B

r1i

A' t '

t

!

~

I

•

!i\) 8'

(b)

Figure 1.6-3 Side view of a capllcitor made from two plates. The capacitor shown in (a) will vary in value do to edge variati®s at points A.A' and B,B'. The capacitor shown in (b) is not sensi1ive to edge variations at B,B '. II is only sensitive to edge variations at points A,A'.

2.6


59

Figure 2.6-4 Illustration of a capacitor

using an octagon to approximate a circle to minimize the ratio of perimeter to

area.

Bottom plare of capacitor

If CuJC1A equals C2p/C2A then CiC1 is determined by the ratios of capacitor area~ only. Thus, the equations show that maintaining a constant area-to-perimeter ratio eliminates matching sensitivity due to the perimeter. lt should not be a surprise that a constant area-toperimeter ratio is achieved when the unit-matching principle is applied! At this point it is worthwhile to ask what geometry is best at maintaining constant area-to-perimeter rati~ square, rectangle, circle, or something else. Referring again to Eq. (2.6-1 0) it is clear that minimizing the perimeter-to-area ratio is a benefit. It is easy to show (see Problem 2.6-4) that a circle achieves the least perimeter for a given area and thus it is the best choice for minimizing perimeter effects. Moreover, a circle has no comers and comers experience more etch variation than do sides. For a variety of reasons unrelated to the technology, circles may be undesirable. A reasonable compromise between a square and a circle is a square with chamfered comers (an octagon) as lllustrated in Fig. 2.6-4. Another useful capacitor layout technique u.~s the Yiunnoulos path.* This method use.<: a serpentine structure that can maintain a constant area-to-perimeter ratio. The beauty of the technique is that you are not limited to integer ratios as is the case when using the unit-matching principle. An example of this layout technique is given in Fig. 2.6-5. It can easily be shown that this structure maintains a constant area-to-perimeter ratio (see Problem 2.6-5).

MOS Transistor Layout Figure 2.6-6 illustrates the layout of a single MOS transistor and its associated side view. Transistors that are used for analog applications are drawn as linear stripes as opposed to a transistor drawn with a bend in the gate. The dimensions that will be important later on are the width and length of the transistor as weU as the area and periphery of the drain and source. lt is the W/L ratio that is the dominant dimensional component governing transistor conduction, and the area and periphery of the drain and source that determine drain and source capacitance on a per-device basis. When it is desired to match transistors. the unit-matching principle and the commoncentroid method should be applied. Once applied, the question arises as to whether the drain/source orientation of the transistors should be mirror symmetric or have the same orientation. In Fig. 2.6-7(a) transistors exhibit mirror symmetry while in Fig. 2.6-7(b) transistors exhibit identical orientation, or photolithographic invariance (PLl).t lt is not uncommon for "1his idea was developed by Aristedes A. Yiannoulos. tlbe term "photol.ithographic invariance~ was coined by Eric 1. Swanson while at Crystal Semiconductor.

60

CMOS TECHNOLOGY

Figure 2.6-5 TheY-path technique

Oneuail

for achieving noninteger capacitor ratios while mainlllining constant area-to-perimeter ratio.

Elcb COII!Jl"noalion

~ Tow area is 12..'1 units

Total area is 18units

the drain/source implant to be applied at an angle. Because of its height (its thickness), polysilicon can shadow the implant on one side or the other, causing the gate-source capacitance to differ from the gate-drain capacitance. By applying the PLllayout method, the effect of the implant angle is matched so that the two Cas are matched and the two Can are matched. In order to achieve both common-centroid and PU layouts, matched transistors must be broken into four units each and laid out in accordance with Fig. 2.6-7(c).

Resistor Layout Figure 2.6-S{a) shows the layout of a resistor. The top view is general in that the resistive component can represent either diffusion (active area) or polysilicon. The side view is particular to Figure 2.6-6 Example layout of an MOS transistor showing top view and side view at the cut line indicated.

Metal

&r-~ . A c~tve area drain/source

I

Polysilicoo

gale/

I ~u!_____

•

. L

------

Active area drain/source Metal L

2.6

Integrated Circuit layout

61

lil~rM r-l.Fftf.1 !·UJJ41·1 l·tkU·UJ ~~

'e1 (b)

(a)

~~f

Metal I

I

I

(d)

(c)

Figure 1.6-7 Example layout of MOS transistors using (a) mirror symmetry, (b) photolithographic invariance, and (c) two transistors sharing a common source and laid out to achieve both photolilhograpbic invariance and common centroid. (d) Compact layout of (c).

the diffusion case. A well resistor is illustrated in Fig. 2.6-8(b). To understand the dimensions that are important in accessing the pedormance of a resistor, it is necessary to review the

relationship for the resistance of a conductive bar. For a conductive bar of material as shown in Fig. 2.6-9, the resistance R is given as (2.6-11)

F!6sc Metal

I

-~

FOX

?:?]

....:1.. """' (wffu•ioa) Well diffusion

~--

(a) D l - or polyoili<:on-

(b) Well roaisk>r

Figure l.6-8 Example layout of (a) diffusion or polysilicon resistor and (b) weD resistor along with their respective side views at the cut line indicated.

62

CMOS TECHNOLOGY

-

Figure 2.6-9

Di=tion of current flow

Cutm~t

flow in conductive bar.

.l..-(__L_w'-~

.1-rr

~-------L--------~

~A

where p is resistivity in 0-cm. and A is a plane perpendicular to the direction of current flow; In of the dimensions given in Fig. 2.6-9, Eq. (2.6-11) can be rewritten as

pL R =WT

(2.6-12}

(fi)

Since the nominal values for p and Tare generally fixed for a given process and material type, they are grouped together to form a new term p, called sheet resistivity. This is clarified by the following expression: R =

(TP) wL= P. wL

(2.6-13)

(0)

It is conventional to give p. the units of !lJ(] (read ohms per square). From the layout point of

view, a resistor has the value determined by the tlllrnher of squares of resistance multiplied byp•• RESISTANCE CALCULATION

Given a polysilicon resistor like that drawn in Fig. 2.6-S(a) with W = 0.8 J.Lm and L = 20 J.LM, calculate p, (in flllJ), the number of squares of resistance, and the resistance value. Assume that p for polysilicon is 9 X 10- 4 fl-cm and the polysilicon is 3000 Athick. Ignore any resistance.

iftMU.j.i First calculate p,.

The number of squares of resistance, N, is L 20 J.LDI N "" W = 0.8 J.LD1 = 2S

giving the total re.o:;istance as

R

=p

1

X

N - 30

X 25 = 750

n

2.6


63

Returning to Fig. 2.6-8, the resistance of each resistor shown is determined by the L/W ratio and its respective sheet resist:ance. One should wonder what the true values of L and W are since, in reality, the cummf flow is neither uniform nor unidirectional. It is convenient to measure L and Was shown and then characterize the total resistance in two components: the body component of the resistor (the portion along the length, L) and the component. One could choose a different approach as long as devices are characterized consistently with the measurement technique (this is covered in more detail in Appendix B on device characterization}.

Capacitor Layout Capacitors can be constructed in a variety of ways depending on the process as well as the particular application. Only two detailed capacitor layouts will be shown here. The double-polysilicon capacitor layout is illustrated in Fig. 2.6-1 O(a). Note that the second polysilicon layer boundary falls completely within the boundaries of the first polysilicon layer (gate) and the top-plate is made at the center of the second poly silicon geometry. This technique minimizes top-plate parasitic capacitance that would have been worsened if the top polysilicon had, instead, followed a path outside the boundary of the polysilicon gate and made to metal elsewhere. Purely digital processes do not generally provide double-polysilicon capacitors. Therefore, precision capacitors are generally made using multiple layers of metal. H only one layer

,, ?if

Metal3

Mellll2 I

(a)

I

Metal I I I

I

(b)

Figure 2.6-10 Hxample layout (a) double-polysilicon capacitor and (b) triple-level metal capacitor along with their respective side views at the cut line indicated.

64

CMOS TE.CHNOLOGY

of metal exists, a metal-polysilicon capacitor can be constructed. For multilayer meta1 processes, polysilicon can still be used as one of the capacitor layers. The problem with using polysiticon as a capacitor layer in this cao;e is that the polysilicon-to-substrate capacitance can represent a substantial parasitic capacitance compared to the desired capacitor. lf the additional parasitic capacitance resuldng from the use of polysilicon is not a problem, greater perunit-area capacitance can be achieved with this type of capacitor. An example of a triple-metal capacitor is illustrated in Fig. 2.6-lO(b). In this layout, the top plate of the capacitor is the metal 2 layer. The bottom plate is made from metals 1 and 3. The value of integrated-circuit capacitors is approximately•

Eox-4

C=-=C t

....

o..-.A

(2.6-14)

ur'

where EQ,. is the dielectric constant of the silicon dioxide (approximately 3.45 X pF/fl.m), tOll is the thickness of the oxide, and A is the area of the capacitor. The value of thecapacitor is seen to depend on the area A and the oxide thickness t.,.,. There is, in addition, a fringe capacitance that is a function of the periphery of the capacitor. Therefore, errors in the ratio accuracy of two capacitors result from an error in either the ratio of the areas or the oxide thickness. If the error is caused by a uniform linear variation in the oxide thickness, then a common-cenrroid geometry can be used to eliminate its effects [34]. Area-related errors result from the inability to precisely define the dimensions of the capacitor on the integrated circuit This is due to the error tolerance associated with making the mask, the nonuniform etching of the material defining the capacitor plates, lllld other limitations [35]. The performllllce of analog sampled-data circuits can directly be related to the capacitors used in the implementation. From the standpoint of analog sampled-data applications, one of the most important characteristics of the capacitor is ratio accuracy [36}.

Layout Rules As the layout of an integrated circuit is being drawn, there are layout rules that must be observed in order to ensure that the integrated circuit is manufacturable. Layout rules governing manufacturability arise, in part, trom the fact that at each mask step in the process, features of the next photomask must be aligned to features previously defined on the integrated circuit Even when using precision automatic alignment tools, there is still some error in alignment. In some ca.o;es, alignment of two layers is critical to circuit operation. As a result, alignment tolerances impose a limitation of feature size lllld orientation with respect to other layers on the circuit. Electrical perfonnance requirements also dictate feature size and orientation with respect to other layers. A good example of this ill the allowable distance between diffusions ing a given voltage difference. Understanding the rules associated with electrical performance is most important to the designer if circuits are to be designed that challenge the limits of the

"This is the infinite parallel plate equation. This expression loses irs acc111'11Cy as !he plate dimensions approach the dimension separating the plates.

2.6


65

technology. The limits for these rules are constrained by the process (doping concentration, junction depth, etc.) characterized undel:" a specific set of conditions. The following set of design rules are based on the minimum dimension resolution X (lambda, not to be confused with the channel length modulation parameter X, which will be introduced in Chapter 3). The minimum dimension resolution Ais typically one-half the min· imum geometry allowed by the process technology. The basic layout levels needed to define a double-metal, bulk. silicon gate CMOS circuit include well (p- or n-). active area (AA), polysilicon-gate (poly), second poly silicon (capacitor top plate), , metal-1, via, metal-2, and pad opening. The symbols for these levels are shown in Fig. 2.6-ll(c). Table 2.6-1 gives the simplified design rules for a polysilicongate, bulk CMOS process. Figure 2.6-11 illustrates these rules. In most ca.'leS design rules are unique to each wafer manufacturer. The design rules for the particular wafer manufacturer should be obtained before the design is begun and consulted during the design. This is especially important in the design of state-of-the-art analog CMOS. However, the principles developed here should remain unaltered while translated to specific processes.

'--------

••••••••

2B

1

38

_j_ -.

SD

J_j_

:;pi! - ~ (a)

It-- -~

itsJl

(b)

Figure 2.6-ll(a) Dlustration of design rules 1-3 ofThble 2.6-1. (b) Illustration of design rules 4 and S of Table 2.6-1.

66

CMOS TECHNOLOGY

2.7 SUMMARY This chapter has introduced CMOS technology from the viewpoint of its use to implement analog circuits. The basic semiconductor fabrication processes were described in order to understand the fundamental elements of this teChnology. The basic fabrication steps include diffusion, irnplantatio11, depositio11, etching, and oxide growth. These steps are implemented by the use of photolithographic methods, which limit the processing steps to certain physical areas of the silicon wafer. The basic processing steps needed to implement a typical silicongate CMOS process were described next. The pn junction was reviewed following the introduction to CMOS technology because it plays an important role in all semiconductor devices. This review examined a step pn junction and developed the physical dimensions, the depletion capacitance, and the voltage-current characteristics of the pn junction. Next, lhe MOS transistor was introduced and characterized wil:h respect to its behavior. It was shown bow the channel between l:he source and drain is formed, and the influence of l:he gate voltage on this channel was discussed. The MOS transistor is physically a very simple component. Finally, the steps necessary to fabricate the transistor were presented. A discussion of possible ive components that can be achieved in CMOS technology followed. These components include only resistors and capacitors. The absolute accuracy

eA

l.. :-·-·-·-·-·· 88 !_._, ___ ,_j .l f' :-·-·-·-·-··,..j I

•

~-·-·-·-·--'

-N-WEU. POLYSnJCON CAPACriUR

;·-·-j MI!TAL-2 L.

-·......- ...

-N-M

-P-M

~ POLYSIUCON----, METAL-I L.:.......:::.. GA'IF. ....___]

;_~]IVATION.

(c)

Figure 2.6-ll(c) IUusiJation of design rules 6-9 of Table 2.6-1.

J2l VIA

2.7

TABLE 2.6-1 Design Rules for a Double-Metal, Double-Polysillcon, n-Well, Bulk CMOS Process Minimum Dimension Resolution 1 n·Well lA. WKith ....................................-. ....................................................................................................................6 lB. Spuci"ll (same polllntial) ............................................................................................................................. 8 IC. Spacin1 (different potential) ........,.....................................................................................................,....... 22 1 Active Ami (AA) 2A. W!dth ............_ .........................................................................- .................................................................4 Spacing l
SA. Siu ............... _ ............. _,, ......................................................... ,.. ,_,..................................................2 ~ 2 58. Spucing........................................................................................................................................................4 SC. Spacing to polysilicon gate .........................................................................................................................2 SO. 8(18dng polysilicon contaet 10 A.A .............................................._,.............................................................2 SE. Metal overlap of .............................................................................................................................. I SF. AA overlap of contaet .................................................................................................................................2 ~. Polysilicon overlap of contae! .....................................................................................................................2 SH. Capacitor top pla\e overlap of ...................- .................................................................................. 2 &. Metal-1 6A. Widlb ...........................................................................................................................................................3 6B. Spa<;ing........................................................................................................................................................ l 1. v... 7A. Si;re ...................................................................................................................................................... 3 X 3 7B. Spacing ........................................................................................................................................................4 7C. Enclosure by Metal· I ..................................................................................................................................2 70. Enclosure by Metal-2 ................................._,, ..... ,_ ..,., ..........,....................................................................2 8. Meud-2 8A. Widlh .............. -. ..........................................................................................................................................4 8B. Spacing........................................................................................................................................................3 &nding Pad 8C. Spacing to AA ...........................................................................................................................................24 80. Spacing to metal circuitry .................................................... _. ................................................. ,................24 8E. Spacing to polysilicon gate ........................_. ...................... _,, __..........................................................24 9. Pllssivotioa Opening (Pad) 9A. Bonding-pad opening ................................. ,........................ _ ..........._,....,............. - ..... 100 jlJ1I X lOll ..,.m 9B. Bonding-pad opening enclosed by Meta1·2 ................................................................................................8 9C. Bonding-pad opening to pad opelling space .............................................................................................40

No1•: For a p-well process, excbange p and n in all instances.

Summary

67

68

CMOS TECHNOLOGY

of these components depends on their edge uncertainties and improves as the components are made physically larger. The relative accuracy of ive components depends on type and layout. The next section discussed further considerations of CMOS technology. These considerations included: the substrate and lateral BITs compatible with the CMOS proce!.!'.; latch-up, which occurs under certain high-current conditions: the temperature dependence of CMOS components; and the noise sources in these components. The last section covered the geometrical definition of CMOS devices. This focused on the physical constraints that ensure that the devices will work correctly after fabrication. This material will lead naturally to the next chapter where circuit models are developed lo be used in analyzing and deg circuit<~.

PROBLEMS 2.1-1. List the five basic MOS fabrication processing steps and give the purpose or function of each slep.

2.3-2. If V58 = 2 V, find the value of VT for then-channel tnmsistor of Example 2.3-1.

2.1-2. What is the difference between positive and negative photol'!ll>ist and bow is photoresist used?

2.3-3. Rederive 'Eq. (2.3-27) given that Vr is not constant in Eq. (2.3-22) but rather varies linearly wiEh l'(y) according to the following equation:

2.1-3. Illustrate the impact on source and drain diffusions of a 7" angle off-perpendicular ion implunt. Assume thai the thickness of polysilicon is 8000 A and that outdiftilsion from point of ion impact is 0.07 ~~om. 2.1-4. What is the function of silicon nitride in the CMOS fabrication proces& described in Section 2.1? 2.1-5. Give typicallhicknesses for the field oxide (FOX), thin oxide (TOX), n ~ or p-, p-well, and metal l in units of j,IJ!l. 2.2-1. Repeat Example 2.2-1 if the applied voltage is- 2 V. 2.2-2. Develop Eq. (2.2-9) using Eqs. (2.2-1 ), (2.2-7), and (2.2-8).

2.2-3. Redevelop Eqs. (2.2-7) and (2.2-8) if the impurity concentration of a pn junction is given by Fig. 2.22 rather than the step junction of Fig. 2.2-l(b). 2.2-4. Plot the normalized reverse current. iltA/iJio versus the reverse vollllge "R of a silicon pn diode that has BV"' IZV and n = 6. 2.2-5. What is the breakdown volmge of a pn junction with NA = N0 = 10 1 ~/cm 3 ? 2.2-4. What change in vD of a silicon pn diode will cause an increase of 10 (an order of magnitude) in the forwatd diode current1 2.3-1. Explain in your own words why the magnitude of the threshold vollage in Eq. (2.3-19) increases as the magnitude of the source-bulk voltage increases (The source-bulk. pn diode remains reverse biased.)

2.3-4. If the mobility of an electron is 500 cm2/(V-s) and the mobility of a hole is 200 cm2/(V-s), compare the performance of an n-channel with a p-channel transistor. ln particular. consider the value of the transconductance parruneler and speed of the MOS tranr.istor. 2.3.5. Using Example 2.3-1 1110 a starting point. calculate the difference in threshold voltage berween two devices whose gate oxide is different by 5% (i.e., t.. '"' 210 A).

=

2.)-6. Repeat Exa111ple 2.3-1 using NA 7 x 10 16 cm-3• 1 gate doping, andN0 l X 10 ~ cm-3 •

=

2.4-1. Given the compoDent tolerances in Table 2.4-1. design the simple low- filter illustrated in Fig P2.4-l to minimize the variation in pole frequency R

:~n___________c___'f'~----~:t FlgurePZ.4-l

Problems over all process variations. Pole frequency should be designed to a nominal value of 1 MHz. You must choose the appropriate capacitQC and resistor type. ~plain your reasoning. Calculate the variation of pole frequency over process using the design you bave chosen. 2.4-2. List two sources of error that can make the actual capacitor, fabricated using a CMOS process, differ from its designed value. 2.4-3. What is the purpose of tbe n + implantation in the capacitor of Fig. 2.4-l(a)?

69

2.4-6. Consider Problem 2.4-5 again but assume thai the o-weU in which R1 lies is not connected to a 5 V supply, but rather is connected as shown in Fig. P2.4-6.

"in

14-4. Consider the circuit in Fig. P2.4-4. Rc.~istor R1 is an n-well resistor witb a nominal value of I0 ldl when the voltage at both terminals is 3 V. The input voltage, v-,.. is a sine wave with an amplitude of 2 VPP and a de component of 3 V. Under these conditions, the value of R1 is given as 2.5-1. Assume v0 = 0.7 V and find the fractional temper-

ature coefficient of 1.• and v0 • 2.5-2. Plot the noise voltage as a function of the frequency

where Room is IOK and tbe coefficient K is the voltage coefficient of an n-weU resistor and has a lllllue of IOK ppm/V. Resistor R2 is an ideal resistor with a value of 10 ldl. Derive a time-domain expression for v..,.. Assume that there are no fre. quency dependencies.

.if the thermal noise is I 00 nVI vl(; and tbe junction of tbe 1/fnoise and thermal noise (the lifnoise comer) is I 0,000 Hz.

2.6-1. Given the polysilicon resistodn Fig. P2.6-l with a

resistivity of p = 8 x Io-4 fi.cm, calculate tbe resistance of !he strutture. Consider only the resistance between conblcl edges. p, = 50 {l/0.

g..__

-

t

Figure 1'2.4-4

Z-4·5. Repeal Problem 2.4-4 using a p+ diffused resistor for R1• Assume that a p+ resistQC's voltage coefficient is 200 ppm/V. The n-well in which R1 lies is tied to a 5 V supply.

5

~~A

5 •

Dil'fw;lnn or polysi:li&:oa millm

Figure P2.6-1 2.6-.Z. Given that you wish to match two transistors having a WIL of I00 IJ.m/0.8 !Jom each. sketch the layout of

these two transistors to achieve the best possible matching.

70

CMOS TECHNOLOGY

2.6-J, Assume tbat the edge Variation of the top plate of a capacitor is 0.05 j.Lm and !bat capacitor top plates are to be laid out as squares. It is desired to nllltch two equal capacitors 10 an IICC111'31.'Y of 0.1 %. Assume mat there is no variation in oxide thickness. How large would the cap~~citors have to be to achieve Ibis matching accuracy? 2.6-4. Show that a circular geometty minimizes perimctet-to-area tatio for a given area requirement. tn your proof, compare against a rectangle and a square. 2.6-S, Show analytically how the Yiannoul05"patb technique illustrated in Fig. 2.6-S maintains a constant area-to-perimeter ratio with non integer ratios. 2.15-6. Design llll optimal layout of a matched pair of transistors having a W/L of 8 IJ.Illll ~-~om. The matching should be photolithographic invarillllt as well as common centroid. 2.6-7. Figure P2.6-7 illustrates various ways to implement lhe layout of a resistor divider. Choose the layout lhat best achieves the goal of a 2:1 ratio. Explain why me other choices are not optilllal.

B r--

1--

;1 A

(8)

~

.!

r--

{b)

~

B

'8

I I I I 1'1 ,._.,

t1

'-'

A

(d)

(e)

IB 2._,.

(e)

Q

I 1------.t ~

A

co

Figure 1'2.6-7

BEFEHEHCES l. Y. P. Tsividis and P. R. Gray, ~A Segmented p2S5 Law PCM Voice Encoder Utilizing NMOS Technology," IEEE J. Solid-Slate Circuli~, Vol. SC-11. No.6. pp. 740-741, Dec. 19'16. 2. B. Fotouhi and D. A. Hodge.;, "High-Resolution AID Conversion in MOSILSI," IEEE J. Solid-State Circuits, Vol. SC-14. No.6, pp. 920-926, Dec. 1979. 3. J. 1. Caves, C. H. Chan, S. D. Rosenbaum, L.P. Sellers, and J.B. Terry, "A PCM Voice Codec with On-Chip Filten," IEEE 1. Solid-State Cirr:uils, Vol. SC-14. No. I. pp. 65-73, Feb. 1979. 4. Y. f Tsividis and P. R. Gray, "An Integrated NMOS Operational Amplifier with Internal Compensation." IEEE J. Solid-State Cin:uits, Vol. SC-I!, No.6, pp. 748-754. Dec. 1916. 5. B. K. Ahuja, P. R. Gray, W. M. Baxter, and G. T. Uehara, "A Programmable CMOS Dual ChaiiDel Jntelfare Processor for Telecommunications Applications,' IEEE J. So/id-Swte Circuits, Vol. SC-19. No, 6. pp. 892--899, Dec. 1984, 6. H. Shirasu, M. Shibukawa, E. Amada, Y. Hasegawa. F. Fujii. K. Yasunari, lllld Y. Toba, "A CMOS SLJC with an Automatic Balancing Hybrid," IEEE J. Solid-State Cirr:uir~. Vol. SC-18, No. 6, pp. 678-684, Dec. 1983. 1. A. S. Grove, Physics and Technology of S~miconductor Devices, New York: Wiley, 1967. 8. R. S. Muller and T. l. Kamins, Device Elec·tronicsfor Integrated Circuits, New York: Wiley. 19n. 9. R. C. Coldaser. Microelectrrmics Pmcessing and De~tice Design. New York: Wiley. 1977. pp. 62-68. 10. S. Wolf and R.N. Tauber, Silicon Pmcessing for 1he VLSI Ero. Sunset Beach, CA: Lattice Press, 1987, p. 27. 11. J. C. Irvin. ~ae.~istl.vity of Bulk Silicon and Diffused Layers in Silicon," Bell Syst. Tech. 1.. Vol. 41. pp. 387-410,

12. 13. 14. 15.

Mar. 1962. D. G. Ong. Modem MOS Ttclmvlogy-Proce:ises, Devices. & Design. New York: McGraw-Hill. i 984, Chap. 8. D. J, Hamilton and W. G. Howard, Basic Integrated Circuit Engineering. New York: McGraw-Hill, 1975, Chap. 2. D. H.l.ee andJ. W. Mayer, "Ion Implanted Semiconductor Devices," Prot:. IEF.E. pp. 1241-125S. Sep1. 1974. J. F. Gibbons, ~Jon Implantation in Semiconductors." Proc. IEEE. Part I, Vol. 56. pp. 295-319, Mar. 1968; Part n. Vol. 60, pp. 1062-1096, Sept. 1972.

References

71

!6. S. WolfandR. N. Tauber, Silicon Proc11ssingjor the VLSI era. Sunset Beach, CA: Lattice Press, 1987, pp. 374-381. 17. S. Wolf and R. N. 'timber, Silicon Processing for rhe VLSI era. Sunset Beach, CA: Lattice Press, 1987, pp. 335-374. 18. J. L Vossen and W. Kem (Eds.), Thin Film Processes. Part lll-2, New York: Academic Press. 1978. 19. P. E. Gise and R. Blanchard, Semiconductor ond lntegriJled Circuit FJJbricotWn Technique. Reston, VA: Reston PuiJ.. lishers,l979, Chap. 5, 6, 10, and 12. lO. R. W. Hon and C. H. Sequin, A Guide to LS//mplememation, 2nd ed. Palo Alto, CA: Xerox Palo Alto Research Cenler, Jan. 1980, Chap. 3. Zt. D. J. Elliot. Integrated Cirruit Fabrican'on Technology. New York: McGraw-Hill, 1982. 22. S. Wolf and R.N. Tauber, Silicon Processing for the VLSI En:~, Sunset Btach, CA: Lattice Press, 1987, pp. 189-191. 23. S. Wolf and R.N. Tauber, Silicon Processing for the VLSI Era, Sunset Bea<:h, CA: Lattice Press,l987, pp. 384-406. 24. P.R. Gray and R. G. Meyer.l\nQ/ysis and De.rign ofAnategrated Cii'Cuits. 2nd ed. New York: Wdey, 1984, Chap. 1. 25. D. A. Hodges and H. G. Jackson, Analysis ond Design of Digitallntegraud Cirruits, New York: McGraw-Hill, 1983. 26. B. R. Chawla and H. K. Gummel. "Transition Region Capacitance of Diffused pn Junctions," IEEE Trans. Electron lkvices, Vol. ED-18, pp. 178-195, Mar. 1971. 11. C. T. Sab, ''Characteristics of the Me!ai-Oxide-Semiconductor TranaisiOf'," IEEE Trans. Electron Det>ice.r, Vol. ED-II, pp. 324-345, July 1964. 28. H. Shichm1111 and D. Hodges, "Modi:ling and Simulation of Insulated-Gate Field-Effect Transistor Switching Circuits,'' IEEEJ. Solid-State Cin:uits, Vol. SC-13, No.3, pp. 285-289. Sept. 1968. l9. J. L. McCreary, "Matching Propcnies, and Voltage and Thmperatlllll Dependence of MOS Capacitors,'' IEEE J, SolidState Circuils, Vol. SC-16, No.6. pp. 608-616, Dec. 1981. 30. D. B. E.~treich and R. W. Dunon, "Modeling Latch-Up in CMOS Integrated Circuits and Systems,'' IEEE Thins. CAD, Vol. CAD-I, pp. 157-162, Oct. 1982. 31. S. M. Sze. Physics of Semiconducwr Devices, 2nd ed New York: Wiley. 1981, p. 28. 32. R. A. Blauschild, P. A. Tucci, R. S. Muller, and R. G. Meyer. 'A New Temperature-Stable Voltage Reference,' IEEE J.

SolitJ.State Cin:uil.l, Vol. SC-19, No.6, pp. 767-774, Dec. 1978. 33. C. D. MotchenbQ{!her and F. 0. Fitchen. Low· Noise Electronic Design. New York: Wiley. 1973. 34. J. L. McCreary and P.R. Gray, "Ail-MOS Charge Redistribution Analog-to-Digital Conversion Thcbniques--Part I,'' IEEE J. Solid-State Circuits, Vol. SC-10, No.6, pp. 371-379. Dec. 1975. JS. J. B. Shyu, G. C. Ternes, and F. Krummenacher, "Random Error Effects in Matched MOS Capacitors and Current Soutces," IEEE J. Solid-State Cin:uits, Vol. SC-19, No.6, pp. 948-955, Dec. 1984. 36. R. W. Brodersen, P.R. Gray. and D. A. Hodges, "MOS Switched-Capacitor Filters," Pro.:. IEEE. Vol. 67, pp. 61-75, Jan. 1979. '!1. D. A. Hodges, P. R. Gray, and R. W. Brodersen, "Potcntia1 of MOS Thchnologies for Anategrated Circuirs," IEEE l Solid·Sttlle Circuits, Vol. SC-8, No.3, pp. 285-294, June 1978.

Chapter 3

CMOS Device Modeling

Before one can design a circuit to be integrated in CMOS technology, one must first have a model describing the behavior of all the components available for use in the design. A model can take the form of ~ru~thematical equations, circuit representations, or tables. Most of the modeling used in this text will focus on the active and ive devices discussed in the previous chapter as opposed to higher-level modeling such as macromodeling or behavioral modeling. lt sbou\d be stressed at the outset that a model is just tbat and no more-it is not tbe real thing! In an ideal world, we would have a model tbat accurately describes the behavior of a devi<:e under all possible conditions. Realistically, we are happy to have a model that predicts simulated performance to within a few percent of measured performance. There is no clear agreement as to whicb model comes closest to meeting this "ideal" model [ 1]. This lack of agreement is illustrated by the fact th.at, at this writing. HSPICE [2] offers the 43 different MOS transistor models from which to choose! This te.x.t will concentrate on only three of these models. The simplest model, which is , appropriate for hand calculations, was described in Section 2.3 and will be further developed here to include capacitance, noise, and ohmic resistance. Jn SPICE terminology, this simple ' model is called the LEVEL I model. Next, a small-signal model is derived from the LEVEL I large-signal model and is presented in Section 3.3. A far more complex model, the SPICE LEVEL 3 model, is presented in Section 3.4. This model includes many effects that are more evident in modem short-channel technologies a.~ well as subthreshold conduction. lt is adequate for device geometries down to about 0.8 p.m. Finally. the BSlM3v3 model is presented. This model is the closest to becoming a standard , for computer simulation. ·

1

1

1

1

Notation SPICE was originally implemented in FOIITRAN where all input was required to be uppercase ASCII characters. Lowercase, greek, and super/subscripting were not allowed. Modem SPICE implementations generally accept (but do not distinguish between) upperca.o;e and lowercase but the tradition of upercase ASCD still lives on. This is particularly evident in the device model parameters. Since greek characters are not available, these were simply speUed out, for example, 'Y entered as GAMMA. Superscripts and subscripts were simply not used. It is inconvenient to adopt the SPICE naming convention throughout the book because equations would appear unruly and would not be familiar to what is commonly seen in the literature. On the other hand, it is necessary to provide the correct notation where application 72

3.1

Simple MOS large-Signal Model {SPICE LEVEL 1)

73

to SPICE is intended. To address this dilemma. we have decided to use SPICE uppercase (nonitalic) notation for all model parameters except those applied to the simple model (SPICE LEVEL 1).

3.1 SIMPLE MOS LHRGE-SIGNHL MODEL [SPICE LEVEL 1] All large-signal models will be developed for the n-channel MOS device with the positive polarities of voltages and currents shown in Fig. 3.1-1 (a}. The same models can be used for the p-channel MOS device if all voltages and currents are multiplied by -1 and the absolute value of the p-channel threshold is used. This is equivalent to using the voltages and currents defined by Fig. 3.1-l{b), which are all positive quantities. As mentioned in Chapter 1, lowercase variables with capital subscripts will be used for the variables of large-signal models and lowercase variables with lowercase subscripts will be used for the variables of small-signal models. When the voltage or current is a model parameter, such as threshold voltage, it will be designated by an uppercase variable and an uppercase subscript. When the length and width of the MOS device is greater than about 10 tJ.m, the substrate doping is low, and when a simple model is desired, the model suggested by Sah f31 and used in SPICE by Shichman and Hodges [4] is very appropriate. This model wa'> developed in Eq. (2.3-27) and is given below. io =

l'oco.L W[ (vas -

Vr) -

(vru)J 2

VDS

(3.1-1)

The terminal voltages and currents have been defined in the previous chapter. The various parameters of Eq. (3.1-1) are defined as 1-1o = surface mobility of the channel for the n-channel or p-channel device (cm2 /V-s)

C.,., = eo• = capacitance per unit area of the gate oxide (F/cm2) 1,..

W

= effective channel width

L

= effective channel length D

D

iu

)

l

ao--:;:--1

+

•cot

VII$

B

)

ip

•os

t

ao---:4

) :~ _) B

~S(:

s

s

(a)

(b)

•w

Figure 3.J.J Positive sign convention for (a) n-channel and (b) p-charuJcl MOS transistor.

74

CMOS DEVICE MODEUNG

The threshold voltage V7 is given by Eq. {2.3-19) for ann-channel transistor: Vr = Vro V70

~)

+ 'Y( V2!.P...j + Vss-

= Vr(Vss

= 0)

V,...lq_e_s;_N_suu-21--P...1

= v.... + 2/¢FJ

+

C

o•

112

'Y = bulk threshold parameter (V ) = ..._

'I'F

(3.1-2)

V2esiqNsua Coo

• ··-" = strong •mvers10n sw.ac:e potenu'a) (V) = -kT ln (NsVB) -q RJ

Vn = flatband VDltage (V)

tPMS =

Q,s Cos

= tPMS -

tPF(substrate) - 1/Jp(gate)

.

kT ....(substrate)= --ln - - [n-channel w1th p-substrate] q n1

t/lr(gate) = - kT In q

(3.1-4)

(3.1-5)

(3.1-6)

[Eq. (2.3-17)]

(Nsua)

(3.1-3)

(NoATE) [n-channel with n polysilicon gate) n1 +

(3.1-7) (3.1-8)

{3.1-9) (3.JLJO)

Q, =oxide-charge= qN.. k =Boltzmann's constant

T = temperature (K) n1 = intrinsic carrier concentration

Table 3.1-l gives some of the pertinent constants for silicon. A unique aspect of the MOS device is its dependence on the voltage from the source to bulk as shown by Eq. (3.1-2). This dependence means that the MOS device must be treated as a four-terminal element. It will be shown later how this behavior can inftuence both the largeand small-signal performance of MOS circuits. TABLE 3.1-1 Constants for Silicon

Constant Sym~

v... k llj

6(f

llsl Boa

Constant DescriptiOn Silicon bandgap (27 "C) Boltzmann's constanr Intrillsic a.rrier conceatration ('rf •C) Pcrlnirrivlty of free space Permittivil}' of silicoa PenniUiv\ly of Si02

Value 1.20S 1.381 X 10·'13

1.4S X 10 10 8.8S4 X L0-14 11.7 6(f 3.9~

Units

v JIK cm- 1 F/cm F/cm F/cm

~.1

Simple MOS Large-Signal Model [SPICE LEVELl]

75

TABLE 3.1·2 Model Parameters for a Typical CMOS Bulk Process Suitable for Hand Calculations Using the Simple Model with Values Based on a 0.8 ..,..m Silicon-Gate Bulk CMOS n-Well Process Typical Parameter Value Parameter Symbol Vro

K'

,.

~

2I.PFI

Parameter Description

n·Channei

Thrc.motd vollage (VII<= 0) Transconductance parameter (in satuf'dl;on) Bulk threshold parameter Channel lenglh modulatioo panuneler Surfa~ potential at strong inversion

0.7 :± 0.1.5 110.0:!:: 10% 0.4 0.04 (l.

0.01 0.7

~

(l. =

I

~~om)

2 ~~om)

p-Channel -0.7:!:. 0.15 so.o:!:: 1()%

0.57 O.ll!i {l. • I ~~om I 0.01 (l. = 2 ~~om) 0.8

Units

v IJ.AN"yllZ

v-• v

In the realm of circuit design, it is more desirable to express the model equations in

of electrical rather than physical parameters. For this reason, the drain current is often expressed as Vos] VJJ$ Vr) - 2

. lo

= fj [ (Vc;s

.

WI (vas- Vr) - 2vvs] Vos = K,L

-

(3.1-11)

or fo

(3.1-12)

where the transconductance parameter (j is given in of physical parameters as (3.1-13)

When devices are characterized in the nonsaturation region with low gate and drain voltages the value for K' is approximately equal to JJoCox in the simple model. This is nol the case when devices are characterized with larger voltages introducing effects such as mobility degradation. For these latter cases, K' is usually smaller. 1Ypical values for the model parameters ofEq. (3.1-12) are given in Table 3.1-2. There are various regions of operation of the MOS transistor based on the model of Eq. (3.1-1). These regions of operation depend on the value of vas- Vr. Ifvc;s- Vris zero or negative, then the MOS device is in the cutoff* region and Eq. (3.1-1) becomes io = 0,

{3.1-14)

In this region, the channel acts like an o-pen circuit. •we will learn later that MOS transistors can operate in the subthreshold region wbere the gate-source voltage is less than the threshold voltage.

76

CMOS DEVICE MODEUNG

Figure 3.1·1 Graphical illusb'lltion of the modi· fied Sah equation.

~m=•...--VT t

t

..........

.•

' '•

.. ' '.•'•• .'•,·---x \•. •'' ' '

-- •,,

''

'

/

./-t.- .... VGS ~....

/"

,.,"'

\

\

' ~stn,g"'"',

,;

'-...

'

t.,

\

\

\

'

\

,

•• '' \ '' ~, '

''

~

0

A plot ofEq. (3.1-1} with)..== 0 as a function of v05 is shown in Fig. 3.1-2 for various values of vas - V1 • At the maximum of these CUTVes the MOS transistor is said to 11aturate. The value of vDS at which this occurs is called the saturation voltage and is given as

(3.1-15)

vw{sat) = vas- Vr

Thus, v05 (sat) defines the boundary between the remaining two regions of operation. If VIJS is less than vos(sat), then the MOS transistor is in the nonsaturated region and Eq. (3.1-1) become.~

io

== K

,Lw[

(V<;s-

. Tvos]

Vr) -

Vo$>

0

< Vos

!!!>

(vas - Vr)

(3.1-16)

In Fig. 3.1-2, the nonsaturated region lies between the vertical axis (vos = 0) and the Vvs = Vas - Vr cUTVe. The third region occurs when Vns is greater than vos(sat) or Vas - V1 • At this point the current i0 becomes independent of "ns· Therefore, v05 in Eq. (3.1-1) is replaced by vDS(sat) of Eq. (3.1-11) to get 0

< (vas- Vr)

~ Vos

(3.1-17)

Equation (3.1-17) indicates that drain current remains constant once vD.~ is greater than v 05 V7' In reality, this is not true. As drain voltage increases, the channel length is reduced, re~;ult\ng in increased current This phenomenon is called channel 141JJglh mod14larion and is ed for in the saturation model with the addition of the factor (1 + >.vn5), where Vos is the actual drain-source voltage and not v05 (sat). The saturation region model modified to include channel length modulation is given in Eq. (3.1-18): 0 < (vGs - Vr) :S Vos

(3.1-18)

3.1

--·-

Simple MOS Large-Signal Model !SPICE LEVEL 1)

~---------- v

G5

I

-V.

77

=1.00

T

Vw VT

•

I

I

' '

0.75

o.so 0.2S

-----------------·

v -

Cutoff Jqlion

0

o.s

1.0

"

vli3"-Vr =O.SO VG.II>-VT G5

v.T

,.-:--- valii- v, 2.0

2.S

=0.00

vllSI(VGlQ-Y.,.l

Figure 3.1·3 Output characteristics of tbe MOS device.

The output characteristics of the MOS transistor can be developed from Eqs. (3.1-14}, (3.1-16), and (3.1-18). Figure 3.1-3 shows these characteristics plotted on a normalized basis. These curves have been normalized to the upper curve, where Va.ru is defined as the value of v0 :; that causes a drain current of I 00 in the saturation region. The entire characteristic is developed by extending the solid curves of Pig. 3.1-2 horizontally to the right from the maximum points. The solid curves of Fig. 3.1·3 correspond to>.= 0. If A 4:-0, then the curves are the dashed lines. Another important characteristic of the MOS transistor can be obtained by plotting i" versus Vcs using Eq. (3.1-18). Figure 3.1-4 shows this result. This characteristic of the MOS transistor is called the transconductance characteristic. We note that the transconductance characteristic in the saturation region can be obtained from Fig. 3.1-3 by drawing a vertical line to the right of the parabolic dashed line and plotting values of i0 versus v0 s. Figure 3.1-4 is also useful for illu.~trating the effect of the source-bulk voltage, v58 • As the value of Vs8 increases,

Flgun:! 3.1-4 Transconduclance characteristic of the MOS transistor as a function of the source-bulk voltage, l'ss-

0

78

CMOS DEVICE MODELING

the value of Vr increases for the enhancement, n-channel devices (for a p-channel device, IVrl increases as v88 increases). V7 also increases positively for !hen-channel depletion device, but since V7 is negative, the value of Vr approaches zero from the negative side. If vs8 is large enough, Vr will actually become positive and the depletion device becomes an enhancement device. Since the MOS transistor is a bidirectional device, determining which physical node is the drain and which the source may seem arbitrary. This is not really the case. For an n-channel transistor, the source is always at the lower potential of the two nodes. For the p-channel transistor, the source is always at the higher potential. It is obvious that the drain and source designations are not constrained to a given node of a transistor but can switch back and forth depending on the tenninlll voltage~ applied to the tranSistor. A circuit version of the large-signal model of the MOS transistor consists of a current source connected between the drain and wurce terminals. that depends on the drain, source, gate, and bulk terminal voltages defined by the simple model described in this section. This simple model has five electrical and process parameters that completely define it. These parameters are K', Vr. 'Y• X and 2411'· The subscript n or p will be used when the parameter refers to an n-channel or p-channel device, respectively. They constitute the LEVEL 1 model parameters of SPICE fS]. 'JYpical values for these model parameters are given ill Table 3.1-2. The function of the large-signal model is to solve for the drain current given the terminal voltages of the MOS device. An example will help to illustrate this as well as show how the model is applied to the p-channel device.

APPLICATION OF THE SIMPLE MOS LARGE-SIGNAL MODEL Assume that the transistors in Fig. 3.1-1 have a W/L ratio of 5 jLm/l !Lffi and that the largesignal model parameters are those given in Table 3.1-2. If the drain, gate, source, and bulk voltages of the n-channel transistor are 3 V, 2 V, 0 V, and 0 V, respectively, find the drain current Repeat for the p-channel transistor if the drain. gate, source, and bulk voltages are -3 V, -2 V, 0 V. and 0 V. respectively.

We must first determine in which region the transistor is operating. Equation (3.1-15) gives v 05 (sat} as 2 V - 0. 7 V == 1.3 V. Since vD.5 is 3 V, the n-channel transistor is in the saturation region. Using Eq. (3.1-18) and the values from Table 3.1-2, we have

.

Jn =

=

K/.W 2L (vas 110

2 VTN) {1

x w-6(5 jLm) l(ljLm)

+ XN vos) 2

(2- 0.7) (I

+ 0.04 X 3) =

520 !LA

Evaluation of Eq. (3.1-15) for the p-channel transistor is given as llso{sat)"" Vsa-

IVrPI = 2 V- 0.7 V =

1.3 V

3.2

Other MOS Large-Signal Model Parameters

79

Since vso is 3 V, the p-channel transistor is also in the saturation region, and Eq. (3.1-17) is applicable. ThedraincurrentofFig. 3. [-l(b) can befoundusingthe values fromTable3.1-2as

.

K;.w

lo = -u-
50

!Vn>D2 (1 + )...,vso)

x~~:~IJ.m) (2-

0.7)2(1

+

0.05 X 3)

= 24311-A

It is often useful to describe vas in of i/) in saturation as shown below: Vus =

Vr +

vu;;ifJ

(3.1-19)

This expression illustrates that there are two components to vGs--an amount to invert the channel plus an additional amount to suppon the desired drain current. This second component is often referred to in the literature as VoN· Thus VoN can be defined as (3.1-20) The term VoN should be recognized as the term for saturation voltage Vns (sat). They can be used interchangeably.

3.2 OTHER MOS LHRGE-SIGNHL MODEL PHRHMETERS The large-signal model also includes several other characteristics such as the source/drain bulk junctions, source/drain ohmic resistances, various capacitors, and noise. The complete version of the large-signal model is given in Fig. 3.2-1. The diodes of Fig. 3.2-1 represent the pn junctions between the source and substrate and the drain and substrate. For proper transistor operation, th~-e diodes must always be reverse biased. Their purpose in the de model is primarily to model leakage currents. These currents are expressed as

.

180

[ (qvso) kT - 1 ]

= 1, exp

(3.2-1)

and (3.2-2) where I, is the reverse saturation cUI'!'ent of a pn junction, q is the charge of an electron, k is Boltzmann's constant. and Tis temperature in kelvin units. The resistors r0 and rs represent the ohmic resistance of the drain and source, respectively. 'JYpically, these resistors may be 50-100 fi* and can often be ignored at low drain currents. •For silicilk process, lhese resislallces will be much leiiS-on the order of 5-l 0 n.

80


Figure 3.2-1 Complete large-signal model for the MOS II'lll1sistor.

B

G

s The capacitors of Fig. 3.2-1 can be separated into three types. The first type jncludes capacitors C80 and C85 , which are a.'!sociated with the back-bia.'!ed depletion region between the drain and substrate and the source and substrate. The second type includes capacitors Cc;0 , Cas. and Ca~~o which are all common to the gate and are dependent on the operating condition of the transistor. The third type includes parasitic capacitors, which are independent of the operating conditions. The dc;pletion capacitors are a function of the voltage across the pnjunction. The expression of this junction-depletion capacitance is divided into two regions to for the high injection effects. The first is given as

Vsx Cax = (CJ) (AX) [ I - PB ]

-MJ

•

vex

s (FC)(PB)

where X= DforC80 orX = SforCBS

AX = area of the source (X = S) or drain (X = D) CJ = zero-bias (v8 x = 0) junction capacitance (per unit area)

qes;Nsua 2PB PB = bulk junction potential [same as
= forward-bias nonidealjunction-capacitance coefficient (::=0.5)

(3.2-3)

3.2 MJ

Other MOS large-Signal Model Parameters

81

= bulk-junction grading coefficient
The second region is given as

C8 x =

(CJ)(AX) [ J+MJ 1 - (1 (1- FC)

Vsx] ,

+ MJ)FC +- MJ PB

VBX

>

(FC)(P8)

(3.2-4)

Figure 3.2-2 illustrates how the junction-depletion capacitances of Eqs. (3.2-3) and (3.2-4) are combined to model the large-signal capacitances C80 and CBS. It is seen that Eq. (3.2-4) prevents C8 x from approaching infinity as v8 x approaches PB. A closer examination of the depletion capacitors in Fig. 3.2-3 shows that this capacitor is like a tub. It has a bottom with an area equal to the area of the drain or source. However, there are the sides that are also part of the depletion region. This area is caUed the sidewaU. AX in Eqs. (3.2-3) and (3.2-4) should include both the bottom and sidewall assuming the zero-bias capacitances of the two regions are similar. To more closely model the depletion capacitance, it is separated into the bottom and sidewall components, given as follows: (CJ)(AX)

(CJSW)(PX)

(~:) ]MJ + [ l - (;~)

Cax = [ l -

Vax :S {FC)(PB)

(3.2-5)

]MJSW•

and C

=

(CJ)(AX) (1 - FC) 1+MJ

BX

[t _

(CJSW}(PX)

+ (1- FC) J+MISW vsx

~

{l

[

+ MJ)FC + MJVsx]

1- (1

PB

Vsx

+ MJSW)FC + PB (MJSW)

]

,

(3.2-6)

{FC)(PB)

Figure 3.2-2 Example of the method of modeling the voltage dependence of the bulk junction capacitances.

'

' ''

'' 0

(FC)(PB)

PB

82

CMOS DEVICE MOOEUNG

Figure 3.2-3 filustration showing tbe bottom (ABCD) and sidewall (ABFE + BCGF + DCGH + ADHE) components of the bulk junction capacitors.

Poi)'Bilicon goue

where

= area of the source (X = S) or drain (X = D) PX = perimeter of the source (X = S) or drain (X = D)

AX

CISW = zero-bias, bulk-source/drain sidewall capacitance

MJSW = bulk-source/drain sidewall grading coefficient Table 3.2-1 gives the values for CJ, CJSW, MJ, and MISW for an MOS device that has an oxide thickness of 140 A resulting in a C0 , = 24.7 X 10-4 F/m2• It can be seen that the depletion capacitors cannot be accurately modeled until the geometry of the device is known, for example, the area and perimeter of the source and drain. However, values can be assumed for the purpose of design. For example, one could consider a typical source or drain to be 1.8 ~~om by 5 J.Lill. Thus, a value for Csx of12.1 F and 9.8 F results for n-channel and p-channel devices, respectively, for Vex = 0. The large-signal, charge-storage capacitors of the MOS device consist of the gate-to-source (Ca5 ), gate-to-drain (CaD), and gate-to-bulk (C08 ) capacitances. Figure 3.2-4 shows a cross section of the various capacitances that constitute the charge-storage capacitors of the MOS

TABLE 3.2-1 Capacitance Values and Coefficients for the MOS Model

Type

p-Channel

n..Channef

Units

CGSO CGDO CGBO

220 )(

220 X 10-IZ 220 X 10-n 700 X 10-oz

F/m F/m F/m F/m2

CJ CJSW MJ MJSW

10-02

220 X 10·-02 700 )( 10.- 02

S60 X IQ-- 6 350 X \1)- 12

o.s 0.3,

770 X 10-<> 381) X 11)- 02 1).5 0.38

Based on an odde lhioknm of 140 A or c,. = 24.7 x

1o·• F/m2•

P/m

3.2


83

Figure 3.14 Large-signal, charge-storage capacitoi'll of lhe MOSdevice.

device. C85 and C8 D are the bulk-to-source and bulk-to-drain capacitors discussed above. The following discussion represents a heuristic development of a model for the large-signal charge-storage capacitors. C1 and C3 are overlap capacitances and are due to an overlap of two conducting sutfaces separated by a dielectric. The overlapping capacitors are shown in more detail in Fig. 3.2-5. The amount of overlap is designated a-c:; LD. This overlap is due to the lateral diffusion of the source and drain underneath the polysilicon gate. For example, a 0.8 j.l.m CMOS process might have a lateral diffusion component, LD, of approximately 16 nm. The overlap capacitances can be approx.imated as (3.2-7) where Welf is the effective channel width and CGXO (X= S or D) ili the overlap capacitance in F/m for the gate-source or gate-drain overlap. The difference between the mask Wand actual W is due to the encroachment of the field oxide under the silicon nitride. Table 3.2-1 gives a value for CGSO and CGDO based on a device with an oxide thickness of 140 A. A third overlap capacitance that can be significant is the overlap between the gate and the bulk. Figure 3.2-6 shows this overlap capacitor (C5 ) io more detail. This is the capacitance that occurs between the gate and bulk at the edges of the channel and is a function of the effective length of the

. I

I

Aclual I ,-L(L ) - ,

1

'

'

off

1 I

I

1..0

' L-----

I I

I

I

I

II

'

L

Bulk

(a)

(b)

Figure 3.2-5 Overlap capacitances of an MOS transistor. (a) Top view showing the overlap between the source or drain and the gate. (b) Side view.

84

CMOS DEVICE MODEUNG

1

Overlap I

,Overlap

1

I

I

''

'

Figure 3.2-6 Gate-bulk overlap capacilllllces.

,..--..I

Gate

Bulk

channel, L.ff· Table 3.2-1 gives a typical value forCGBO for a device based on an oxide thickness of 140 A. If the device illustrated in Fig. 3.2-4 was in the saturated state, the channel would ell.tend almost to the drain and would extend completely to the drain if the MOS device were in the nonsaturated state. c2 is the gate-to-channel capacitance and is given as

(3.2-8) The term L.tr is the effective channel length resulting from the mask-defined length being reduced by the amount of lateral diffusion (note that up until now, the symbols Land W were used to refer to "effective" dimensions whereas now these have been changed for added clarification). C4 is the channel-to-bulk capacitance, which is a depletion capacitance that will

vary with voltage like Css or C8 tJ. lt is of interest to examine Cas. Cas. and Con as v0 s is held constant and Vas is increased from zero. To understand the results, one can imagine following a vertical line on Fig. 3.1-3 at, say, v05 = 0.5(V050 - V7 ), as v0 s increases from zero. The MOS device will first be off until Vas reaches Vr. Next, it will be in the saturated region until vc;s becomes equal to vru{sat) + Vr- Finally, the MOS device will be in the nonsaturated region. The approximate variation of CoB> CGSt and C00 under these conditions is shown in Fig. 3.2-7. In cutoff, there is no channel Capacitance

C1+ ic2

c.+ 4c2

,__ "·-~ _,.

___

"'""-~-.-

c()li

l--------------' cGS' eGo v

....... _

~DS" CODS!BDI

c,... c,,

Ceo CGB

'

- .... ----------·

-Off-

"

)

-saruralion---.

'T

v63 = 0

....... V.

"w•

T

NOD·

-

~IIIUI'ataon

Figure 3.1-7 Voltage dependence of CGs. CoD> and C08 as a function of Va.s with Vos constant and V63 = 0.

3.2


8S

and C08 is approximately equal to C1 + 2C5• As v0 s approaches Vr from the off region. a thin depletion layer is formed, creating a large value of C4 • Since C4 is in series with C2, Httle effect is observed. As vas increases, this depletion region widens, causing C4 to decrease andreducing Cell· When Vc;s = VT, an inversion layer is formed that prevents further decreases of c4 (and thus C08). C., C2, and C3 constitute Cas and CoD· The problem is how to allocate C2 to Cas and Cav· The approach used is to assume in saturation that approximately two-thirds of C2 belongs to Cas and none to C00. This i~;, of course, an approximation. However, it ha.~ been found to give reasonably good results. Figure 3.2-7 shows how Cas and C00 change values in going from the off to the saturation region. Finally, when v08 is greater than v08 + Vr; the MOS device enters the nonsaturated region. [n this case, the channel extends from the drain to the source and C2 is simply divided evenly between Cav and Ccs as shown in Fig. 3.2-7. As a consequence of the above considerations, we shall use the following formulas for the charge-storage capacitances of the MOS device in the indicated regions.

Off (3.2-9a) (3.2-9b}

(3.2-9<;)

Saturation C08 = 2Cs = CGBO <4«)

(3.2-lOa)

(3.2-IOb) (3.2-lOc)

Nonsaturated CGs = 2C5

= CGBO (L..rr)

(3.2-lla)

(3.2-llb)

= (CGDO

+ 0.5CoxL.rr>W.rr

(3.2-J lc)

86


Equations that provide a smooth transition between the three regions can be found in the literature 16]. Other capacitor parasitics associated with transistors are due to interconnect to the transistor, for example, polysilicon over lield (substrate). This type of capacitance typically constitutes the major portion of CGs in lhe nonsaturated and saturated regions and thus is very imponant and should be considered in the design of CMOS circuits. Another important aspect of modeling the CMOS device is noise. The existence of noise is due to the fact that electrical charge is not continuous but is carried in discrete amounts equal to the charge of an electron. In electronic circuits, noise manifests itself by representing a lower limit below which electrical signals cannot be amplified without significant deterioration in tlte quality of the signal. Noise can be modeled by a current source connected in parallel with i0 of Fig. 3.2-1. This current source represents two sources of noise, called thennal noise and flicker noise [7,8]. These sources of noise were discussed in Section 2.5. The meansquare current-noise source is defined as .2 _ [ 8kTgm(l

,, -

3

+ 11) • +

(KF)lo] 2

/CaxL

llf

(A2)

(3.1-12)

where llf = a small bandwidth (typically I Hz) at a frequency f '11

= g,Mg, (see Eq. (3.3-S)J

k =Boltzmann's conslallt

T = temperature (K) 6m = small-signal transconductance from gate to channel [see Eq. (3.3-6)1 KF = flicker noise coefficient (F-A)

f

= frequency (Hz)

KF has a typical value of 10- 28 F-A. Both sources of noise are process dependent and the values are usually different for enhancement and depletion mode field effect transistors (FETs). The mean-square current noise can be reflected to the gate of the MOS device by dividing F.q. (3.2-12) by g~. giving

(3.2-13) The equivalent input-mean-square voltage-noise form of Eq. (3.2-13) will be useful for analyzing the noi
Small-Signal Model for the MOS Transistor

3.3

87

~'

lc-14

le-1-4

p-channel

D-i:baancJ

J

le-18

~

le-20

~

le-16

le-16 lg=6mA

J

~

10 =2mA

le-18 le-10

~..II:

lc-22

le-22

te-24

le-24 10

lk

100

IOk

lOOk

10

IM

100

It

IOk lOOk

IM

FrequeiiCy (IU)

fmtuency (lh)

(b)

(a)

Figure 3.2-8 Drain-current noise for (a) llll a-channel and (b) a p-cbannel MOSFET measured on a

silicon-gate submicron process. (at the given bias conditions).* Consequently. in many practical cases, the equivalent inputmean-square voltage noise of Eq. (3.2-13) is simplified to 2.

eeq

-···

=

[

2f Cm.KFWLK' ] !J.f

2

(3.2-14)

(V )

or in of the input-voltage-noise spectral density we can rewrite Eq. (3.2-14) as 1

eeq =

2 eeq

KF

tJ.f = 2/ Cox Wl.K'

=f

B WL

2

(V 1Hz)

(3.2-15)

where B is a constant for an n-channel or a p-channel device of a given process.** The righthand expression of Eq. (3.2-15) will be important in optimizing the design with respect to noise performance.

3.3

SMHLL-SIGNRL MODEL FOR THE MOS TRANSISTOR Up to this point, we have been considering the large-signal model of the MOS transistor shown in Fig. 3.2-1. However, after the large-signal model has been used to find the de conditions, the small-signal model becomes important. The small-signal model is a linear model that helps to simplify calculations. It is only valid over voltage or current regions where the large-signal voltage and currents can adequately be represented by a straight line. Figure 3.3-l shows a linearized small-signal model for the MOS transistor. The parameters of the small-signal model will be designated by lowercase subscripts. The various parameters of this small-signal model are all related to the large-signal model parameters and •If the bias current is reduced, lbe thermal noise floor increases, thus moving lbe lif noise comer to a lower frequency. Therefore, lbe lif noise comer is a function of !he lbermal noise floor. ••Since the same symbol is u.'!Cd for voltage (current) noise and vol!age (c~nt) spwtral density. the units are generaUy used to distinguish the difference if it is noL clear in the text.

88

CMOS DEVICE MODEUNG

Figure 3.3-1 Small-signal model of the MOS transistor.

B

G

s

de variables. The normal relationship between these two models assumes that the small-signal parameters are defined in term.~ of the ratio of small penurbations of the large-signal variables or as the partial differentiation of one large-signal variable with respect to another. The conductances Sbd and g6, are the equivalent conductances of the bulk-to-drain and bulk-to-source junctions. Since these junctions are normally reverse biased, the conductances are very smalL They are defined as iJiso . . Sbd = -~(evaluated at the qwescent pomt) 63£ iJVso

0

(3.3-1)

iJiss . . 81>• = --(evaluated at the qutescent pornt) s; 0 iJvss

(3.3-2}

and

The channel conductances g,., Smb.P and Sr~> are defined as . ) g,. = iHo(evaluated at the. qutescent pomt

(3.3-3)

iJio . • = -(evaluated at the qutescent pomt) iJvss

(3.3-4)

-a\Ius

8mb.r

and a~

.

.

8dl = -,.-(evaluated at the qwescent pomt)

""ns

(3.3-5)

3.3. Small-Signal Model for the MOS Transistor

89

The values of these small-signal parameters depend on which region the quiescent point occurs in. For example, in the saturated region g., can be found from Eq. (3.1-18) as (3.3-6) which emphasizes the dependence of the small-signal parameters on the large-signal operating conditions. The small-signal channel transconductance due to v58 is found by rewriting Eq. {3.3-4) as (3.3-7) Using Eq. (3.1-2) and noting that atD/iJVr = -aiofavas. we get* 1'

(3.3-8)

This transconductance will become important in our small-signal analysis of the MOS transistor when the ac value of the source-bulk potential v.., is not zero. The small-signal channel conductance, gd, {g0 ), is given as (3.3-9)

The channel conductance will be dependent on L through )., which is inversely proportional to L. We have assumed the MOS transistor is in saturation for the results given by Eqs. (3.3-6), (3.3-8), and (3.3-9). The important dependence of the small-signal parameters on the large-signal model parameters and de voltages and current~ is illustrated in Thble 3.3-1. In this table we see that the three small-signal model parameters of g,. Kmm. and Kd• have several alternate fonns. An example of the typical values of the small-signal model parameters follows.

TYPICAL VALUES OF SMALL-SIGNAL MODEL PARAMETERS Find the values of Km• Km~n. and R.u using the large-signal model parameters in Table 3.1-2 for both an n-channel and a p-channel device if the de value of the magnitude of the drain current is 50 f.LA and the magnitude of the de value of the source-bulk voltage is 2 V. Assume that tbe WIL ratio is 1 j.~.m/1 tJ.rn.

•Note that absolute signs are used for V88 in order to prevent g- from becoming infinite. However, in a few rare cases the soiii'CHulk junction is forward biased and in this case the absolute signs must be removed and Vs8 becomes negative (for n-channel transistor).

90


TABLE 3.3-1 Dependence of the Small-Signal Model Parameters on the de Values of Voltage and Current in the Saturation Region Small-Signal Model Parameters B..

de Current .. (2K' (D Wfl-) 112

I

de Voltage K'W L ')'[fj(VGJ- V7)] 112

""-(Vos- Vr) "'t(2Jo(J)lfl

g.., lr.t.

de Current and Voltage

2<211/1.1 + jv..,!)tlf

2(2\4> ;\

+

IVsail ill

s>.lo

Using the values of Table 3.1-2 and Eqs. (3.3-6), (3.3-8), and (3.3-9) gives g,., = 105 fJ.A/V, 70.7 fJ.AIV, 8m~n

Bm~n ~ 12.8 11-A/V, and 8.ts = 2.0 ILA/V for then-channel device and Bm = 12.0 ~/V, and B.ts = 2.5 JJ.A/V for the p-channel device.

=

Although MOS devices are not often used in the nonsaturation region in analog circuit design, the relationships of the small-signal model parameters in the nonsaruration region are given as (3.3-10)

(3.3-11) and 8rb e fJ(Vas- Vr- V~)

(3.3-12)

Table 3.3-2 summarizes the dependence of the small-signal model parameters on the largesignal model parameters and de voltages and currents for the non saturated region. The typical values of the small-signal model parameters for the nonsaturated region are illustrated in tbe following example.

TYPICAL VALUES OF THE SMALL-SIGNAL MODEL PARAMETERS IN THE NONSATURATED REGION Find the values of the small-signal model parameters in the nonsaturation region for an n-channel and a p-channel transistor if Vas = 5 V, Vos =' l V, and IV851 ""' 2 V. Assume that the WIL ratio for both transistors is 1 p.m/1 p.m. Also assume that the value forK' in the nonsaturation region is the same as that for the saturation (generally a poor assumption}.

3.3

Small-Signal Model for the MOS Transistor

91

TABLE 3.3-2 Dependence of the Small-Signal Model Parameters on the de Values of Voltage and Current in the Nonsaturation Region Small-Signal Model Parameter:s

de Voltage and/or current Dependence

2(21~,1

+ 1Vsall112

•I!(Vn.,- Vr- Vlls)

Solution First, it is necessary to calculate the threshold voltage of each transistor using Eq. (3.1-2). The results are a Vr of 1.02 V for the n-channel and -1.14 V for the p-channel. This gives a de current of 383 j.LA and 168 j.LA, respectively. Using Eqs. (3.3-10), (3.3-11). and (3.3-12), we get Km = 110 ~J.A/V, Cmru = 13.4 ~J.A/V, and r.u = 3.05 kil for then-channel transistor and 8m = 50 IJ..A/V, 8mru = 8.52 j.LA/V, and rtb = 6.99 kO for the p-channel transistor. The values of rd and r:. are assumed to be the same as r0 and rs of Fig. 3.2-1. Likewise, for small-signal conditions C8., Csd• C~~· Cbd, and C"" are evaluated for Cv, CBd• and C8 , by knowing the region of operation (cutoff, saturation or nonsaturation) and for Cbd and Cbs by knowing the value of V11o and Vns· With this infonnation, C8,, C11d• C8b• Cbd, and Cb, can be found from Cus. Cuo· Ca 8 • Cso• and Css. respectively. If the noise of the MOS transistor is to be modeled, then three additional current sources are added to Fig. 3.3-1 as indicated by the dashed lines. The values of the mean-square noisecurrent sources are given as

i~rD = ( 4 ::)Af i~rS = (~;)A/

(A2)

(3.3-13)

(Al)

(3.3-14)

and (3.3-15) The various parameters for these equations have previously been defined. With the noise modeling capability, the small-signal model of Fig. 3.3-1 is a very general model. It will be important to be familiar with the small-signal model for the saturation region developed in this section. This model. along with the circuit simplification techniques given in Appendix A, will be the key element in analyzing the circuits in the following chapters.

92

3.4


COMPUTER SIMULATION MODELS The large-signal model of the MOS device previously discussed is simple to use for band cal· culations but neglect~ many important second-order effect~. Wbile a simple model for hand calculation and design intuition is critical, a more accurate model is required for computer simulation. There are many model choices available for the designer when choosing a device model to use for computer simulation. At one time, HSPICE"' ed 43 different MOSFET models [2] (many of which were company proprietary) while SmartSpice publishes for 14 [9). Whlcb mndel is the right one to use? In the fabless semiconductor environment, the must use the model provided by the wafer foundry. Jn companies where the foundry is captive (i.e., the company owns its own wafer fabrication facility) a modeling group provides the model to circuit designers. It is seldom that a designer cbOO$ell a model and performs parameter extraction to gel the for the model chosen. The SPICE LEVEL 3 de model will be covered in some detail because it is a relatively straightforward extension of the LEVEL 2 model. The BSJM3v3 model will be introduced but the detailed equations will not be presented because of the volume of equations required to describe it-there are other good texts that deal with the subject of modeling exclusively {10,11], and there is little additional design intuition derived from covering the details. Models developed for computer simulation have improved over the years but no model has yet been developed that, with a single set of parameters, coveis device operation for all possible geometries. Therefore, many SPICE simulators offer a feature called •·model binning:• Parameters are derived for transistors of different geometry (W's and l.'s) and the simulator detennines which set of parameters to use based on the particular Wand L called out in the device instantiation line in the circuit description. The circuit designer need only be aware of this since the binning is done by the model provider.

SPICE LEVEL 3 Model The large-signal model of the MOS device previously discussed is simple to use for hand calculations but neglects many important second-order effects. Most of these second-order effects are due 10 narrow or short channel dimensions (le.-;s than about 3 p.m). ln this section, we will consider a more complex model that is suitable for computer-based analysis (circuit simulation, i.e., SPICE simulation). In particular, the SPICE LEVEL 3 model will be covered (see Table 3.4-1}. This model is typically good for MOS technologies down to about 0.8 ~~om. We will also consider the effects of temperature on the parameters of the MOS large-signal model We first consider second-order effects due to small geometries (Fig. 3.4-1 ). When Vas is greater than V11 the drain current for a small device can be given a.~ {2] follows:

Drain Current

.

[

'os =BETA Vas-

w.lf

(l+ft,)]

Vr- - 2

VoE llo£

w.rr

BETA= KP.. "cox4Ir = ... .L..rr •HSP(CE is now owned by Avant! Inc:. and has been n:named Star-H.spice.

(3.4-1)

(3.4-2)

3.4

Computer Simulation Models

93

TABLE 3.4-1 Typical Model Parameters Suitable for SPICE Simulations Using LEVEL-3 Model (Extended Model)* Typical Parameter Value Parameter

Sym6ot

Parameter OescripCI'on

vro

Threshold Mobility Narrow-width threshold adjustment factor Static- threshold adju.•tment factor Saturation field factor In channel length m~Jdulalion Mobility degradation factor Subs!rate doping Oxide lhickne~;s Melllllurgicaljunction deplh Delta width Lareral diffusion Psrameter for weak inversion modeling

uo DELTA El'A

KAPPA THETA

NSUB TOX XJ WD

LD NFS

coso

rr-Chtmnel

CGDO

-0.7:!: 0.15

v

660 2.4

210

t:m 1N-s

1.25

0.1

0.1

0.15

2.5

0.1 3 X 1016

0.1 6 x 1016

140

140

em-' A

0.2

0.2

J.Ull

0.016 7 X 1011

0.015 6 X IOH

:220 X 10-la :220 X 10-11

:220 X 10- 12 220 x

IN IN

J.Ull

100 110

CJ CJSW MJ MJSW

l.hriU

0.7:!: 0.15

x w-• 2 x w-• Jso x w- 12

CGBO

p-Ch«mree

0.5 0.38

w-••

700 X 10-IZ

560 X 10"6 350 X 10-lt

)1.111

cm- 2 F/m

Flm Flm P/m2 F/m

0.5

0.35

"The-o;e values ate based on a 0.8 J.Ull silicon-gate bulk CMOS n-well process and include capacitance parame1en1 from Table 3.2-1.

I..., = L - 2{LD)

(3.4-3)

w.lf = w -

2(WD)

(3.4-4)

min(vru.., vos(sat))

(3.4-5)

GAMMA ·f. fn + 4(PHI + vss) 112

(3.4-6}

lfoe

=

1" =

Gate

Bulk

Figure 3.4-1 Illustration of tbe shortchannel effects in rbe MOS transistor.

94


Note that PHI is the SPICE model term for the quantity 2(/)p. Also be aware that PHI is always positive in SPICE regardless of the transistor type (p- or n-cbannel). In this tellt, the term PHI will always be positive while the term 2(/)p will have a polarity determined by the tr.msistor type as shown in Table 2.3-1. fn =DELTA

w.a J;

•

=

(3.4-7)

l- 4rr XJ{LD XJ+we[ l - ( XJ+wp wp

wp = xd(Plfl xd=

TBs;

2·C.,. 2 112

) ]

_

LD} XJ

(3.4-8)

+ "ss) 112

(3.4-9)

2. e. )112 51 ( q • NSUB

(3.4-10)

(3.4-11)

kt = 0.0631353,

kl = 0.08013292,

k3 = 0.011 10777

Threshold Voltage Vr

= V~n -

ETA- 8.14 X 10-22 ) (

c....

3 ~

. Vns

+ GAMMA· /.(PHI + Vss) 112 + /n{PHI +

(3.4-12) llss)

(3.4-13)

or vbl

= vro -

GAMMA ·

VPHl

(3.4-14)

Saturation Voltage Vw

VDs(sat)

v,s- Vr = 1 + fb =

vc =

v.., +

Vc-

(3.4-15)

(v;.. + ~~~)'

12

-·

VMAX · l.,ff p;.

lfVMAX is not given, then v00 (sat)

(3.4-16) (3.4-17)

~

v001 •

3.4

Computer Simulation Models

95

Effective Mobility

II

" -

I

~

UO

when VMAX = 0

,.., - 1 +THETA (vGI- V7)'

{3.4-18)

p,

v • when VMAX > 0; otherwise l'ctt = p..

P..ff =

(3.4-19)

1+~ Vc

Channel Length Modulation

ti.L = xd [KAPPA (vDs- vDS(sat))]'12, tiL=

ep

~xJl + [

ep ~Jy +

when VMAX

=0

{3.4-20)

J

12

KAPPA· xtf (vDS- VDs(sat))

,

(3,4-21)

whenVMAX>O where Vc (vc

ep =

+ Vos (sat))

(3.4-22}

L.tt VDS (sat}

.

iDs

los=

1

(3.4-23)

_ tJ.

The temperature-dependent variables in the models developed so far include the Fermi potential, PHI, EO, bulk junction potential of the sourc~ulk and drain-bulk junctions, PB, tbe reverse currents of the pn j'unctions, / 8 , and the dependence of mobility on remperacure. The temperature dependence of most cf these variables is found in the equations given previously or from well-known expressions. The dependence of mobility on temperature is given as UO(T} = UO(T0)

T)BBX ( To

(3.4-24)

. where BEX is the temperature exponent for mobility and is typically -1.5. llthorm

kT q

(3.4-25)

(T) " " -

EG(T)

PHI(T) = . 'T} _

vbl\

[r + ~:os.o] T) [3 In (ToT) + PHI(To) . (

= 1.16- 1.02 • 10-• To

. ,.,.

- VIR\•o}

+

- vlhernlo ( T}

PHJ(T)- PIU(T0)

2

+

(3.4-26)

EG(T0 ) EG( T) ] vobonD (To) - vtherm ( T)

EG(T0 ) - EG(T) 2

(3.4-27)

(3.4-28)

96

CMOS DEVICE MODfLING

VTO(T) =

vbl {T)

+ GAMMA[ VPHJ(

T)]

(3.4-29)

(NSUB)

(3.4-30)

PHI(7) = 2v~~>orm In ni.,T)

n/..T)

= 1.45 · 1016 (!:._) T

312

exp[EG ·

0

(.!.1) ( I ) To 2 • vlheml (To)

(3.4-31)

For drain and source junction diodes, dle following relationships apply:

(T) -

PB(T) = PB · To

( (T)

EG(T0 )

EG(T) ]

v~~~mn (T) 3 In To + vlllonn (To) - v......., (T)

(3.4-32)

and ls (T)

<=

Is (To) . N

ex.pr EG(To)

v.....,(To)

_

EG(T) (T)

Vthonn

+ 3 ln(I..)] To

(3.4-33)

where N is the diode emission coefficient. The nominal temperature, To. is 300 K. An alternate form of the temperature dependence of the MOS model can be found elsewhere [l2].

BSIM 3v3 Model MOS transistor models introduced thus far in this chapter bave been used successfully WMn applied to 0.8 ).l.ffi technologies and aoove. As geometries shrink. below 0.8 p.m, better models are required. Researchers in the Electrical Engineering and Computer Seiences Department at The University of California at Berkeley have been leaders in the developement of SPICE and the models used in it. In 1984 they introduced the BSIMI model [13] to address the need for a better submicron MOS transistor model. The BSlMl nwdel approached the modeling problem as a multiparameter curve-fitting exercise. The model contained 60 parameters covering the de performance of the MOS transistor. There was some relationship to device physics, but in a large pan, it was a nonphysical model. Later. in 1991, UC Berkeley released the BSIM2 model that improved perfonnance related to tbe modeling of output resistance changes due to hot-electron effects, source/drain parasitic resislallce, and inversion-layer capacitance. This model contained 99 de parameters, making it more unwieldy than the 60-parameter {de parameters) BSlMl model. In 1994, UC Berkeley introduced tbe BSIM3 model (version 2), which, unlike the earlier BSIM models, returned to a more device-physics-based modeling approach. The model is simpler to use and has only 40 de parameters. Moreover, the BSIM3 model provides good performance when applied to analog as well as digital circuit simulation. In its third version, BSIM3v3 rt 4], it has bec::ome the industry standard MOS transistor model. The BS1M3 model addresses the following important effects seen in deep-submicron MOSFET operation: • • • •

Threshold voltage reduction Mobility degradation due to a vertical field Velocity saturation effects Drain-induced baai.er lowering (DffiL)

3.5

a

LEVELl

•

J..EVEL3

9

BSJM3v~

Subthreshold MOS Model

97

WIL~2010.8

6

4

v,.,..=2.i

2

0

2

4

Figure 3.4-2 Simulation of MOSFET tr.m.scondoctance characteristic using LEVEL = 1, LEVBL = 3 and the BSIM3v3 models.

• • • •

Channel length modulation Subthreshold (weak inversion) conduction Parasitic resistance in the source and drain Hot-electron effects on output resistance

The plot shown in Fig. 3.4-2 shows a comparison of a 20/0.8 device using the LEVEL 1, LEVEL 3, and BSIM3v3 models. The model parameters were adjusted to provide similar characteristics (given the limitations of each model). Assuming that the BSIM3v3 model closely approximates actual transistor performance, this figure indicates that the LEVEL I model is grossly in error, while the LEVEL 3 model shows a significant difference in modeling the transition from the nonsaturation to linear region.

3.5

SUBTKRESHOLO HOS MODEL The models discussed in previous sections predict that no current will ftow in a device when the gate-source voltage is at or below the threshold voltage. In reality, this is not the case. As vqs approaches V7 , the iD - v05 characteristics change from square-Jaw to exponential.

98


Whereas the region where Vas is above the threshold is called the strong inversion region, the region below (actually, the transition between the two regions is not well defined as will be explained later) is called the subthrt!slwld. or weak irlvenion region. This is illustrated in Fig. 3.5-1 where the transconductance characteristic of a MOSFET in saturation is shown with the square root of current plotted as a function of the gate-source voltage. When the gate-source voltage reaches the value designated as VON (this relates to the SPICE model formulation), the current changes from square-law to an exponential-law behavior. It is the objective of this section to present two models suitable for the subthreshold region. The first is the SPICE LEVEL 3 [2] model for computer simulation while tbe second is useful for hand calculations. In the SPICE LEVEL 3 model, the transition point from the region of strong inversion to the weak inversion characteristic of the MOS device is designated as VoN and is greater than Vr. VoNisgivenby V0 ,.. = Vr +fast

(3.5-1)

where

_ kT[ 1

fast - q

q · NFS + COX

+

GAMMA·/. (PHI+ Vse) 1n +/,(Pill + Vss>] 2(PHT

_

+ vs8 )

(

3'5 2)

NFS is a parameter used in the evaluation of VoN and can be extracted from measurements. The drain current in the weak inversion region, Vas< VoN• is given as

.

IDS

.

= IDS (VoN• \IDE• Vse) exp

(VosVaN) fast

(3.5-3)

where ios is given as [from Eq. (3.4.1), with Vm replaced with V01,]

.

ros

[

(1 +'b) ]

=BETA. VoN- Vr- - 2

VIJE

•

(3.5-4)

Voe

llltMJ

Weak

1000.0

..p;

inVel'i\iOfl

"'glon

Siron&

inversia11

HIO.O

"'&ion 10.0 1.0

0

V7

VIIH

vG.J

U

\11

VON

Vas

Figure 3.5-l Weak inversion characteristics of the MOS transistor as modeled by Eq. (3.5-4).

3.6

99

SPICE Simulation of MOS Circuits

Figure 3.5-l The three regions of operation of an MOS transistor.

Moclcrau! inversion region

+ Weak lnven;ioo

1000.0

Sln!llg

lnvenlion

100.0

region

111.0

r.o .___ ___.;.....__..___,._____ 0

For hand calculations, a simple model de.'>Cribing weak inversion operation is given as

•

W

lo a; L loo exp

"'

(Vo.r) n(kT/q)

(3.5-5)

where the term n is the subthreshold slope factor, and 100 is a process-dependent par-.nneter that is dependent also on vs11 and V7• These two are best extracted from experimental data. '!Ypically n is greater tbaa 1 8lld less than 3 (1 < n < 3). The point at whicb a transistor enters the weak inver$ion region can be approximated as kT

"••< V7 + nq-

(3.5-6)

Unfortunately, the model equations given here do not properly model the transistor as it makes the transition from strong to weak inversion. In reality, there is a transition region of operation between strong and weak inversion called the "moderate inversion" region (15]. This is illustrated in Fig. 3.5-2. A complete treatment of the operation of the ttansistorthrough this region is given in the literature fl5,16]. It is important to consider the temperature behavior of the MOS device operating in the subthreshold region. As is the case for strong inversion, the temperature coefficient of the threshold voltage is negative in the subthreshold region. The variation of current due to temperature of a device operating in weak inversion is dominated by the negative temperature coefficient of the threshold voltage. Therefore, for a given gate-source voltage, subthreshold current increases as the temperature increases. This is illustrated in Fig. 3.5-3 [17). Operation of the MOS device in the subthreshold region is very important when low· power circuits are desired. A whole class of CMOS circuits have been developed based on the weak inversion operation characterized by the above model [ 18-21]. We will consider some of these circuits in later chapters.

3.G SPICE SIMULRTIOI OF MOS CIRCUITS The objective of this section is to show how to use SPICE to the perfonnance of an MOS circuit. It is assumed that the reader already has experience using SPICE to simulate circuits containing resisto!'ll, capacitors, source.~, and so on. This section will elltend the reader's

100

CMOS DEVICE MODEUNG

Figure 3.5·3 Transfer characteristics of a loog-cbannet device as a function of temperature. (Cupyrigbl © /977}.

lo-4

to"" i0

cAJ

IIY

L=9jlm W/l.;9.7

1

V0 =0.1

YBS=O

to-•o to·•2 -0.2

0

0.2 vGS

0.4

0.6

0.8

(volts)

knowledge to include the application of MOS b'ansiBtors into SPICE simulations. The models used in this seclion are the LEVEL I and LEVEL 3 models. In order to simulate MOS circuits in SPICE, two components of the SPICE simulation file are needed. They are instance declarations and model descriptions. Instance declarations are simply descriptions of MOS devices appearing in the circuit along with cbaracteristics unique to each instance. A simple example tbat shows the minimum required for a transistor instance follows:

M1 ! 6 ? 0 NCH W=100U L:1U Here, the first letter in the instance declaration, M, tells SPICE that the instance is an MOS transistor (ju.~t like R tells SPICE that an instance is a resistor}. The 1 makes this instance unique (different from M2, M9 9, etc.) The four numbers following Ml specify the nets (or nodes) to which the drain, gate, source, and substrate (bulk) are connected. These nets have a specific order as indicated below:

M <SOURCE> . • . Following the net numbers, is the model name governing the character of the particular instance. In the example given above, the model name is NCR. There must be a model description somewhere in the simulation file that describes the model NCH. The transistor width and length are specified for the instance by the w "' 1 0 o u and L = 1 u expressions. The default units for width and length are meters so the U following the number 100 is a multiplier of 10-<>. (Recall that the following multipliers can be used in SPICE: M, u, N. P. F, for 10"3, 10"6 , 10"9 , 10" 12• 10" 1 ~. respectively.) Additional information can be specified for each instance. Some of these are:

Drain area and periphery (AD .and PD) Source area and periphery (AS and P s) Drain and source resistance in squares (NRD and NRS)

3.6

SPICE Simulation of MOS Circuits

101

Multiplier designating how many devices are in parallel (M)

Initial conditions (for initial transient analysis) Drain and source area and periphery are used in calculating depletion capacitance and diode currents (, the drain and source are pn diodes to the bulk or well). The numbers of squares of resistance in the drdin and source (NRD and NR s) are used to calculate the drclin and source resistances for the tram;istor. The multiplier designator is very important and thus deserves extended discussion here. In Section 2.6 layout matching techniques were developed. One of the fundamental principles described was the ''unit-matching" principle. This principle prescribes that when one device needs to be M times larger than another device, then the larger device should be made from M units of the smaller device. In the layout, !he larger device would be drawn using M copies of the smaller device-all of them in parallel (i.e., all of the gates tied together, all of the drains tied together, and all of the sources tied together). In SPICE, one must for the multiple component~ tied in parallel. One way to do this would be to instantiate the larger device by instantiating M of the smaller devices. A more convenient way to handle this is to use the multiplier parameter when the larger device is instantiated. Figure 3.6-l illustrates two methods for implementing a 2X device (unit device implied). In Fig. 3.6-l(a) the correct way to instantiate the device in SPICE is

Ml 3 2 1 0 NCH W=20U L=lU whereas in Fig. 3.6-1 (b) the correct SPICE instantiation is

Ml 3 2 l

0 NCH W=lOU

~=lU

M=2

Figun:3.6-1 (a)Ml 3 2 1 0 NCH W 20U L = lU.~)Ml 3 2 1 0 NCH W = lOU L = lU M = 2.

=

• • • • • •

...

r-

• • • ~

•

• ~

±

I ~~n__ .___....,

(a)

J

~

(b)

102

CMOS DEVICE MODEUNG

Clearly, from the point of view of matching (again, it is implied that an attempt is made to achieve a 2:1 ratio), case (b) is the better choice and thus the instantiation with the multiplier is required. For the salce of completeness. it should be noted that the following pair of instan· , tiatioos are equivalent to the use of the multiplier: M1A 3 2 1 0 NCH W=lOU L=lU MlB 3 2 1 0 NCH W=lOU L=lU

Some SPICE simulators offer additional further describing an instance of a MOS transistor. A SPICE simulation file for an MOS circuit is incomplete without a description of the model to be used to characterize lhe MOS transistors used in the circuit. A model is described by placing a line in the simulation file using the following format: .MODEL <MODEL NAME> <MODEL TYPE> <MODEL PARAMETERS>

The model line must always begin with . MODEL and be followed by a model name such as N c H in our example. Following the model name is the model type. The appropriate choices for model type in MOS circuits is either PMOS or NMOS. The final group of entries is model parameters. If no entries are provided, SPICE uses a default set of model parameters. Except for the crudest of simulation.~. you will always want to avoid the default parameters. Most of the time you should expect to get a model from the foundry where the wafers will be fabricated, or from the modeling group within your company. For times where it is desired to check hand calculations that were performed using the simple model (LEVEL 1 model) it is useful to know the details of entering model information. An example model description line follows • . MODBL NCH NMOS LEVEL=l VTD=l KP=50U GAMMA=0.5 +LAMBDA=O.Ol

In this example, the model name isNCH and the model type is NMOS. The model parameters dictate that the LEVEL\ model is used with V'J' o, KP, GAMMA, and LAMBDA specified. Note that the + is SPICE syntax for a continuation line. The information on the model line is much more extensive and will be covered in this and the following paragraphs. The model line is preceded by a period to flag the program that this line is not a component. The model line identifies the model LEVEL (e.g., LEVEL=l) and provides the electrical and process parameters. If the does not input the various parameters, default values are used. These default values are indicated in the 's guide for the version of SPICE being used (e.g .. SmartSpice). The LEVEL 1 model parameters were covered in Section 3.1 and are the zero-bi.a.~ threshold voltage, VTO (Vrol. in volt~ extrapolated to io = 0 for large devices; the intrinsic transconductance parameter, KP (K'), in amperes/volt2; the bulk threshold parameter, GAMMA (-y) in volt 112 : the surface potential at strong inver.;ion. PHI (2r/JF), in volts; and the channel length modulation parameter, LAMBDA()\), in volt- 1• Values for these parameters can be found in Table 3.1-2.

3.6

Spice Simulation of MOS Circuits

103

Sometimes, one would rather Jet SPICE calculate the above parameters from the appropriate process parameters. This can be done by entering the surface state density in em - 2 (NSS}, the oxide thickness in meters (TOX), th.e surface mobility, UO {#£o), in cm21V·s, and the substrate doping in em- 3 (NSUB ). The equations used to calcuJate the electrical parameters are q(NSS)

VTO = .PMS - (e.,JTOX) +

(2q · ss; • NSUB • PHI) 112

(e.,.ITOX)

e.,,

+ PHI

(3.6-1)

(3.6-2)

KP =UOTOX (2q • s 51 • NSUB) 112 GAMMA = (e.,.,/TOX)

(3.6-3)

and

PHI= 12-PFI

2kT = l n (NSUB) -q

n,

(3.6-4)

LAMBDA is not calculated from the process parameters for the LEVEL 1 model. The constants for silicon, given in Table 3.1-1, are contained within the SPICE program and do not have to be entered. The next model parameters considered are those that were considered in Section 3.2. The first parameters considered were associated with the bulk-drain and bulk-source pnjunctions. These parameters include the reverse current of the drain-bulk or source-bulk junctions in A (lS) or the reverse-current density of the drain-bulk or source-bulk junctions in A/m2 (JS). JS requires the specification of AS and AD on the model line. lf IS is specified, it overrides JS. The default value of IS is usually 1o- 14 A. The next parameters considered in Section 3.2 were the drain ohmic resistance in ohms (RD), the source ohmic resistance in ohms (RSJ. and the sheet resistance of the source and drain in ohms/square (RSH). RSH is overridden if RD or RS is entered. To use RSH, the values of NRD and NRS must be entered on the model line. The drain-bulk and source-bulk depletion capacitors can be specified by the zero-bias bulk junction bottom capacitance in farads per m 2 of junction area (CJ). CJ requires NSUB and assumes a step junction using a formula similar to Eq. (2.2-12).Altemately, the drain-bulk and source-bulk depletion capacitances can 'be specified using Eqs. (3.2-5) and (3.2-6). The necessary parameters include the zero-bias bulk-drain junction capacitance (CBD) in farads, the zero-bias bulk-source junction capacitance (CBS) in farads, the bulk junction potential (PB) in volts, the coefficient for forward-bias depletion capacitance (FC), the zero-bias bulk junction sidewall capacitance (CJSW) in farads per meter of junction perimeter, and the bulk junction sidewall capacitance grading coefficient (MJSW). IfCBD or CBS is specified, then CJ is overridden. The values of AS, AD, PS, and PD must be given on the device line to use the above parameters. "JYpical values of these parameters are given in Thble 3.2-1. The next parameters discussed in Section 3.2 were the gate overlap capacitances. These capacitors are specified by the gate-source overlap capacitance (CGSO) in farads/meter, the gate-drain overlap capacitance (CGDO) in farads/meter, and the gate-bulk overlap capacitance (CGBO) in farads/meter. Typical values of these overlap capacitances can be found in

104


Table 3.2· I. Finally, the noise parameters inc1ude the flicker noise coefficient (KF') and the flicker noi~ exponent (AF}. Typical values of these parameters are 10- 28 and l, respectively. Additional parameters not discussed in Section 3.4 include the type of gate material (TPG) •. the thin oxide capacitance model flag, and the coefficient of channel charge allocaled to the drain (XQC). The choices for TPG are + 1 if the gate material is opposite to the substrate, -1 if the gate material is the same as the substrate, and 0 ir the gate material is aJu. minum. A charge-controlled model is used in the SPICE simulator if the value of the parameter XQC has a value smaUer than or equal to 0.5. This model attempts to keep the sum of charge associated with each node equal to zero. If XQC is larger than 0.5, charge conservation is not guaranteed. In order to illustrate its use and to provide examples for the novice to follow, several examples will be given showing how to use SPICE to perfonn various simulations.

USE OF SPICE TO SIMULATE MOS OUTPUT CHARACTERISTICS

1

Use SPICE to obtain the output characteristics of then-channel transistor shown in Fig. 3.6-2 using the LEVEL 1 model and the parameter values of Table 3.1-2. The output curves are to be plotted for drain-source voltages from 0 to 5 V and for gate-source voltage.-; of 1, 2, 3, 4, ' and 5 V. Assume that the bulk voltage is zero. Figure 3.6-2 Circuit for Example 3.6-1.

+ VDS

vas

lfiMU.J 1M Table 3.6-1 shows the input file for SPICE to solve this problem. The first line is a title for the simulation file and must be present. The lines not preceded by ":• define the interconnection of the circuit. The second line describes bow the transistor is connected, defines the model to be TABLE 3.6-1 SPICE Input File for Example 3.6-1 EX. 3.6-l Use of SPICE to Simulate MOS Output Ml 2 1 0 0 MOSl W•SU L~l.OU VDS 2 0 S VGS 1 0 1 .MOD~L MOSl NMOS VT0=0.7 KP•l10U GAMMA=0.4 LAM8DA=0.04 PHI=0.7 ,DC VDS 0 S 0.2 VGS 1 S l .PRINT DC V(2} I(VDS) .END

3.6


105

used, and gives thew and L values. Note that because the units are meters, the suffix u is used to convert to j.Lm. The third and forth lines describe the independent voltages. vns and VG s are used to bias the MOSFET. The fifth line is the model description for MI. The remaining lines instruct SPICE to perform a de sweep and print desired results.. DC asks for a de sweep. In this particular case, a nested de sweep is specified in order to avoid seven consecutive analyses. The . cc . . . line will set VGS to a value of 1 V and then sweep VDS from 0 to 5 V in increments of0.2 V. Next, it will increment VGS to 2 V and repeat the vns sweep. This is continued until five VDS sweeps have been made with the desired values of VGS. The • PRINT • • • line directs the program to print the values of the de sweeps. The last line of every SPICE input file must be •END 11. Figure 3.6-3 shows the output plot of this analysis. Figure 3.6-3 Output from Example 3.6-1.

0

0.5

1.0

1.5

2.0

2.S

vos

3.0

3.5

~.0

._, ,.0

<.....l

DC ANALYSIS OF FIG. 3.6-4 Use the SPICE simulator to obtain a plot of the value of VoUT as a function of VJN of Fig. 3.6-4. Identify the de value of vm that gives VoUT = 0 V. Figun: 3.6-4 A simple MOS amplifier for Example 3.6-2.

106

CMOS DEVICE MODEUNG

The input file for SPICE is shown in Table 3.6-2. It follows the same fonnat as the previ0111 example except that two typeS of transistors are used. These models are designated by MO SN and MO s P. A de sweep is requested starting from VJN = 0 V and going to +5 V. Figure 3.6-S shows the resulting output of the de sweep. TABLE 3.6-2 SPICE Input File for Example 3.6-2 Bx. 3.6-2 OC Analysis of Fig. 3.6-4 Ml 2 1 0 0 MOSN w~su L=lO M2 2 3 4 4 MOSP w~so L~lU M3 3 3 4 4 MOSP w~su L~lU Rl 3 0 lOOK VD1> 4 0 DC 5,0

VIN 1 0 DC 5.0 .MODEL MOSN NMOS VT0~0.7 KP=llOU GAMMA=0.4 LAMBOA=0.04 PBI=0.7 .MODEL MOSP PMOS VT0=-0.7 KP=SOU GAMMA=0.57 LAMBDA=0.05 PHI=0.8 .DC VIN 0 S Q.l .PRINT DC V(21 .END 5.0 ....---~,-----------.

Flgun:3.6-5 Output of Example 3.6-2.

. ~.o.

-

2.0

. 1.0 -

. '-...,

0.0

Q

'

0-'

'

1.0

1

1-'

'

2.0

'

4.$

'

'

3.0 3-' ....- J

.

• '.,

-4.0

5.1)

AC ANALYSIS Of FIG. 3.6-4 Use SPICE to obtain a small-signal frequency response of Vou1(w)/V;n(w) when the amplifier is biased in the transition region. Assume that aS pF capacitQris attached to the output of Fig. 3.6-4 and find the magnitude and phase response over the frequency range of J00 Hz to 100 MHz.

lfiMit.J,; The SPICE input file for this example is shown in Table 3.6-3.1tis important to note thatV'IN has been defined as both an ac and a de vQltage source with a de value of 1.07 V, If the de

3.6


107

TABLE 3.6-3 SPICE Input File for Example 3.6-3 Ex. 3.6-3 AC Analysis of Fig. 3.6-4 M1 2 1 0 0 MO~ W=SU L:lU M2 2 3 4 4 MOSP W"SU L=lU M3 3 3 4 4 MOSP W=SU L=lU

CL 2 0 5P Rl 3 0 lOOK VDD 4 0 DC S.CI

VIN 1 0 DC 1.07 AC 1.0 .MODEL MOSN NMOS VTO 2 0.7 KP • 1100 GAMMA~ 0.4 LAMBDA~ 0.04 PHI : 0.7 .MODEL MOSP PMOS VTO" -0.7 KP z SOU GAMMA" 0.$7 LAMBDA= 0.05 PHI~ 0.8 .AC DEC 20 100 lOOMEG

.OP .PRINT AC VM(2) V0Bf2) VP{2l • J;:Nl)

voltage were not included, SPICE would find the de solution for VIN = 0 V, which is not in die transition region. Therefore, the small-signal solution would not be evaluated in the transition region. Once the de solution has been evaluated, the wnplitude of the signal applied as the ac input has no influence on the simulation. Thus, it is convenient to U.'le ac inputs of unity in order to treat the output as a gain quantity. Here, we have assumed an ac input of 1.0 V peak. Tbesimulationdesiredisdefinedbythe .AC DEC 20 100 lOOMEG line. This line directs SPICE to make an ac analysis over a log frequency with 20 points per decade from 100Hz to 100 MHz. The • o P option has been added to print out the de voltages of all circuit nodes in order to that the ac solution is in the desired region. The program will calculate the linear magnitude, dB magnitude, and phase of the output voltage. Figures 3.6-6{a) and 3.6-6(b} show the magnitude (dB} and the phase of this simulation.

2Q

0

-10 .2()

·30

+ ........,..,......,....,.,_.............,_......"'T"",........""''"..........,..,.

IW II•

I kHz

10 -It<

IIIII klfz

I Mil•

IQ Mill IIIII Mlft

10011<

I kHz

IokHz

lOOkHz ~

(b)

F1gure 3.6-6 (a) Magnitllde response and (b) phase response of Example 3.6-3,

lloffi<

IOMit< IOOiolll<

108

CMOS DEVICE MODEUNC

TRANSIENT ANALYSIS OF FIG. 3.6-4 The last simulation to be made with Pig. 3.6-4 is the transient response to an input pulse. This simulation will include the 5 pF output capacitor of the previous example and will be made from time 0 to 4 11-s.

lf!'IMit.l,i Table 3.6-4 shows me SPICE input file. The input pulse is described using the piecewise linear capability (PWL) of SPlCE. The output desired is defined by . T:RAN 0 • 0 1 U 4u which asks for a transient analysis from 0 to 4 J.LS at points spaced every 0.01 J.LS. The output will consist of both VJN(t) and v0 (.,7 (f) and is shown in Fig. 3.6-7. The use of an a.~terisk at the beginning of a line causes that line to be ignored.

Table 3.6-4 SPICE Output for Exampl-e 3.6-4 Ex. 3.6-4 Transient Analysis of Fig. 3.6-4 Ml 2 1 0 0 MOSN WmSU L=lU M2 2 3 4 4 MOSP W=~O L=lU Ml 3 3 4 4 MOSP W=SU L=lU CL 2 0 SP Rl 3 0 lOOK VOD 4 0 OC 5.0 VIN l 0 PWL(O OV lU OV 1.05U JV JU 3V 3.050 OV 6U QV)

*VIN 1 0 DC -1.07 AC 1.0 ,MODEL MOSN PHI "' 0.7 .MODEL MOSP PHI = 0.8 .Til.AN 0.010 .PRINT TRAN .END

0. 7

PMOS VTO

-0.7 KP •

KP

4.0

-

v~

v\

----------

-

I I

~

I I

t.o o.s -

r

I

I I

1 I I

I I I

I 0.0 ~

o.s'

I

~

11 OU GAMMA "' 0 , 4 LAMBDA "' 0. 04

·sou

GAMMA •

0.57 LAMBDA"' 0.05

4U V(.<) V(l)

s.o

-

=

NMOS VTO

u

r... t...l

'

~

'

u

'

~

u'

~

Figure 3.6-7 Transient response of fuample 3.6-4.

3.7

Summary

109

The above examples will serve to introduce the reader to the basic ideas and concepts of using the SPICE program. In addition to what the reader has distilled from these examples, a useful set of guidelines is offered, which has resulted from extensive experience in using SPICE:

1. Never use a simulator unless you know the range of answers beforehand. 2. Never simulate more of the circuit than is necessary. 3. Always use the simplest model that will do the job. 4. Always start a de solution from the point at which the majority of the devices are on. 5. Use a simulator in the same manner as you would make the measurement on the bench. 6. Never change more than one parameter at a time when using the simulator for design. 7. Learn the basic operating principles of the simulator so that you can enhance its capability. Know how to use its options. 8. Watch out for syntax problems like 0 and 0. 9. Use the correct multipliers for quantities .

.10. Use common sense. Most problems with simulators can be traced back to a violation of one or more of these guidelines. There are many SPJCE simulators in use today. The discussion here focused on the more general versions of SPICE and should apply in most cases. However, there ill nothing fundamental about the syntax or use of a circuit simulator, so it is prudent to carefully study the manuel of the SPICE simulator you are using.

3.7 SUMMARY This chapter bas tried to give the reader the background necessary to be able to simulate CMOS circuits. The approach used bas been based on the SPICE simulation program. This program normally has three levels of MOS models that are available to the . The function of models is to solve for the de operating conditions and then use this information to develop a linear small-signal model. Section 3.1 described the LEVEL 1 model used by SPICE to solve for the de operating point. This model also uses the additional model parameters presented in Section 3.2. These parameters include bulk resistance, capacitance, and noise. A small-signal model that was developed from the large-signal model was described in Section 3.3. These three sections represent the basic modeling concepts for MOS transistors. ModeL~ for computer simulation were presented. The SPICE LEVEL 3 model, which is effective for device lengths of 0.8 IJ.ffi and greater, was covered. The BSIM3v3 model, which is effective for deep-submicron devices, was introduced. Large-signal models suitable for weak inversion were also described. Further details of these models and other models are found in the references for this chapter. A brief background of simulation methods wa'l presented in Section 3.6. Simulation of MOS circuits using SPICE was discussed. After studying this chapter, the reader should be able to use the model information presented along with a SPICE simulator to analyze MOS circuits. This ability will be very important in the remainder of this text. It will be used to intuitive design approaches and to perform analyses

110

CMOS DEVICE MODEUNG

beyond the scope of the techniques presented. One of the important aspects of modeling is to determine the model parameters thai best fit the MOS process being used. Appendix B will be devoted to this subject.

PROBLEMS 3.1-1. Sketch to scale the output charac:teristics of an enhancement n-channel device if Vr = 0.7 V and 10 = 500 p.A when Vos =- 5 V in sat.uration. Choose values of Vas = 1, 2, 3, 4, and 5 V. Assume that the channel modulation parameter is zero. • 3.1-2. Sketch to scale the output characteristics of an enhancement p-channel device if Vr = -0.7 V and lo = -500 11-A when Vas = -5 V in saturation. Choose values of Vas = -I, -2. -3. -4. and -6 V. Assume that the channel modulation parameter is

zero. 3.1-3.ln Table 3.1-2, why is "'fp greater than 'YN for a n-well, CMOS technology? :1.1-4. A large-signal model for the MOSFET that features symmeli)' for the drain and source ill given as

3.2-2. And Csx at Vu = 0 V and 0. 75 V of Fig. P3.2-2 the values or Table 3.2-1 apply to the MOS device, where FC = 0.5 and PB = 1 V. Assume the device is n-cbannel and repeat for a p-channel device.

r--l.61J.m ____.,

r

l

+--"

• • • •

~

~ ,1.-;:;............_

"-• • '

io = K' : !Hvos - Y.,;ful.vm - VTS)}

Metal

/

I

T

. Polysilicon

'

2

- [( va.D - vro) u (Van - Vro) I

where u(A:) is I if x is greater than or equal to zero and 0 if xis less than zero (step function) and V1x is the lhresbold voltage evaluated from the gate to X. where X is either S (source) or D (drain), Sketch this model in the form of i 0 versus Vns for a constant value of Vas (vas> VTS) and identify the saturated and nonsarurated region.~. Be sure to extend this sketch for both positive and negative values of vo,s. Repeat the sketch of 10 versus vns for a constant value of Voo {Vao > V'Tl]). Asswne that both vll' and Vro are positive. J.l-5. Equations (3.1-12) and (3.1-18) describe the MOS model in the nonsaturation and saturation region, respectively. These equations do not agree at the point of transition between saturation and noJISaW· ration regions. For hand calculations. this is not an issue. but for computer analysis, it is. How would you change Eq. (3. H 8) so that it would agree with Eq. (3.1-12) at vos = v0 s(sat)? 3.2-1. Using the values ofTables 3.1-1 and 3.2-l,calculate the values of CGB. CGS, and CGD for a MOS device that has a W of 5 f.Ll1l alld an L of I p.m for all lhree regions of operation.

"

"

Active Area

2.0 lllll

08).1m

Figure P3.2-2

3.2-3. Calculate the values of CaBo Co.~. and Coo for an n-channel device with a length of 1 11-m and a width of S tJ.ffi. Assume V0 "" 2 V, VG = 2.4 V. and Vs"" 0.5 V and let V8 = OV. Use model parameters from Tables 3.1-1, 3.1-2, and 3.2-1. 3.3-1. Calculate the transfer function 1'011,(s)/v;.(s) for the circuit shown in Fig. P3.3-l. The WIL of Ml is 2 11-m/0.8 14m and the W!L of M2 is 4 I-Lml4jLm.

Wll.=210.8

Figure P3.3-l

Problems NOll: that this is a small-signal analysis and the input voltage ha.~ a de value of 2 V. .3.3-2. Design a low- filter patterned after the circuit in Fig. P3.3-l that achieves a -3 dB frequency of 100kHz. U-3. Repeat Examples 3.3-1 and 3.3-2 if the WIL ratio is 100 jLlll/10 )I.Ill. U-4. Find the complete small-signal model for an ncbannellrllnsistor with the drain at 4 V, gate at 4 V, source at 2 V, and the bulk at 0 V. Asswne the model parameters from Thbles 3.1-1. 3.1·2. and 3.2-1, and WIL = I 0 jiJil/1 fLliL 3.3-5. Consider the circuit in Fig P3.3-S. It is a parallel connection of n MOSFET transistors. Each transistor bas the same length, L. but each transistor can have a different width, W. Derive an expression for Wand L for a single transistor that replaces, and is equivalent to, the multiple parallel !raDSistors.

111

3.5-1. Calculate the value for VON for an NMOS transistor in weak inversion a.~suming thatfs andfn can be approximated to be unity ( 1.0). 3.5-2. Develop an expression for the small signal transconductance of a MOS device operating in weak inversion using tbe large signal expression of Eq. (3.5-5). 3.5-3. Another way to appro11imate the transition from strong inversion to weak inver.~ion is to find the current at which tbe weak inversion lrBnsconducrance and the strong inversion transconductance are equal. Using this method and the approximation for drain current in weak inversion (Eq. (3.5-5)). derive an expression for drain current at the lransition between strong and weak inversion. 3.6-1. Consider the circuit illustrated in Fig. P3.6-1. (a) Write a SPICE netlist that describes this circuit. (b) Repeat part (a) with M2 being 2 jJJtl/1 p..m and M3 and M2 are ratio matched, 1:2.

.-----T""""---.. ----- ... !Ill

Figure P3.3-S

"3.3-6.

Consi~r tbe circuit in Fig 3.3-6. It is a series connection of 11 MOSFET transistors. Each rransistor has the same width, W. but each tmnsiRtor can have a different length. L. Derive an expression for Wand L for a single transisior that replaces, and is equivalent to, the multiple parallel transistors. When using the simple model. you must ignore body effect.

~~r-, •0 •••

.

•I •• •

.

Figure P3.3-6

Figure P3.6ol 3.6-2. Use SPICE 10 perform the following analyses

on the circuit shown in Fig. P3.6-l: (a) Plot vOUT versus "'N for the nominal parameter set shown. (b) Separately, vary K' and Vr by + 10% and repeat part (a)-four simulations. Parameter

n·Channel

p-Channel

Vr

0.7

-0.7

J('

llO

so

0.04

0.05

Units

!.6-3. Use SPICE to plot i 2 as a function of v2 when i 1 has values of 10. 20, 30, 40. :50, 60, and 70 J,lA for Fig. P3.6-3. The maximum value of v2 is S V. Use the model parameters of Vr = 0.7 V and

112

CMOS DEVICE MODEUNG

K' = 110 p.AN2 and )\. = 0.01 v-•. Repeat wilb ll.-= o.04v-•. 3.6-4. Use SPICE ro plot i0 as a function of vns for values of v05 "' 1. 2. 3, 4 and 5 V for ann-channel tmnsistor wirh V7 "' 1 V. K' = 110 p.AN2• and A= 0.04 v-•. Show how SPICE can be used to generale and plot these curves simultaneously as illustratm

W/1. = 10 j.lm/2jlm

Figure P3.6-3

by Pig. 3.1·3. 3.6-5. Repeat E!xample 3.6-J if the transistor of Fig. 3.6-2 is a PMOS having the model parameters given in Table 3.1-2. 3.6-6. Repeat Exnmple~ 3.6-2 through 3.6-4 for the circuit of Pig. 3.6-4 if Rl = 200 itO.

REFERENCES \. Y. Tsividis, "Problems with Modeling of Analog MOS LSI,'" IEDM, pp. 274-277. 1982. 2. Star-Hspice 's ManUJJI. Fremont, CA: Avant! 2000. 3. C. T. Sah, "CbatliCteristics of the Metal-Oxide-Semiconductor Transistor,'' IEEE Tran.s. Electron Devices, ED-11, No.7, pp. 324-345, July 1964. 4. H. Shichrnan and D. Hodges, "Modelling and Simulation oflnsulated-Grue Field-Effect Transistor Switching Circuil.5," fEf.t; J. Solid·Slille Circuit!, Vol. SC-3, No. 3. pp. 285-2.89. Sept. 1968.

5. A Vlndimerescu, A. R. Newton, and D. 0. Pederson, SPICE Version 2G.O 's Guide, University of California, Berkeley, Sept. 1980. 6. D. R. Alexander. R. J. Antinone. and G. W. Brown, SPICE Modelling Handbook. Repon BDM/A-77-071-TR, BDM Corporation, 2600 Yale Blvd.. Albuquerque, NM 87106. 7. P. R. Gray and R. G. Meyer, Analysis and Design ofAnategrated Circuits, 2nd ed. New York: Wiley, 1984, p. 646. 8. P. E. Allen and E. Sancbez·Sinencio, Switched Capacitor Circuits. New York: Van Nostrand Reinhold, 1984, p. 589. 9. SmartSpice Modeling Manual. Vols. 1 and 2. Santa Clara. CA.: Sil' r the BSIM Model, Electronics Research Laboratory, UniversitY of California, Berkeley, CA 94720. Memorandum No. UCBIERL M84J99, November21, 1984. 14. Y. Cheng and C. Hu, MOSFET Modeling & BSIM3 's Guide, Norwell, MA: K\uwer Academic Publishets, 1999. 15. Y. Tsividis, "Moderale Inversion in MOS Devicc!l," Solid State Electron .• Vol. 25, No. 11, pp. 1099-1104, 1982. 16. P. Anrognelti. D. D. Olviglia, and B. Profumo. ~cAD Model for Threshold and Subthreshold Conduction in MOSFET's,"IEEE J. Solid-State Circ:uil$, Vol. SC-17, No.2. pp. 454-458. June 1982. 17. S. M. S:u:, Physics ofSemiconductor Devices, 2nd ed. New York: Wiley, 1981. 18. E. Vinoz and J. Fellrath, "CMOS Anategrated Circuits Based on Weak Inversion Operation," IEEE J. Solid-State Ci~uits, Vol. SC-12, No.3, pp. 231-244, June 1977. 19. M.G. DeGrauwe, J. Rigmcnants, E. V1ttoz, and H. J. DeMan. "Adaplive Biasing CMOS AmplifieTS," IEEE J. SolidState Circuits, Vol. SC-17, No. 3. pp. 522-528, June 1982. 20. W. Steinhagen and W. L. Engl. "Design of Integrated Analog CMOS Circuil'I-A Multichannel Telemetry Transmitter," JEEEJ. Solid·Stare Circuits. Vol. SC-13, No.6, pp. 799-805, Dec. 1978. 21. Y. Tsividis and R. Ulmer, "A CMOS Voltage Refercm:e," IEEE J. Solid·State Circuits, Vol. SC-13, No.6,

pp.774-778,Dec.1978.

t~apter 4

Rnalog CMOS Subcircuits From the viewpoint of Table 1.1-2, the previous two chapters have provided the back~ ground for understanding the technolo-gy and modeling of CMOS devices and components compatible with the CMOS process. The next step toward our objective-methodically developing the subject of CMOS analog circuit design-is to develop subcircuits. These simple circuits tonsist of one or more transistors and generally perform only one function. A subcircuit is typically combined with other simple circuits to generate a more complex cir· cuit function. Consequently, the circuits of this and the next chapter tan be considered as building blocks. The operational amplifier, or op amp, to be covered in Chapters 6 and 7, is a good example of how simple circuits are combined to perform a c:omplex function. Figure 4.0-1 presents a hierarchy showing how an operational amplifier-a complex circuit-might be related to varioUil simple circuits. Working ollf way backward, we note that one of the stage$ of m op amp is the differential amplifier. The differential amplifier consists of simple circuits that might include a current sink, a current-mirror load, and a source-coupled pair. Another stage of the op amp is a second gain stage, which might consist of an inverter and a current-sink load. If the op amp is to be able to drive a low-impedance load, an output stage is necessary. The output stage might consist of a source follower and a current-sink load. It is also necessary to provide a stabilized bias for each of the previous stages. The bia<>ing stage could consist of a current sink and current mirrors to distribute the bias currents to the other stages. The subject of basic CMOS analog circuits has been divided into two chapters to avoid one lengthy chapter and yet provide sufficient detail. Chapter 4 covers the simpler subcircuits, including the MOS switch, active loads, current sinks/sources, current mirrors and current amplifiers, and voltage and current references. Chapter S will examine more complex circuits like CMOS amplifiers. That chapter represents a natural extension of the material presented in Chapter 4. Taken together, these two chapters are fundamental for the analog CMOS designer's understanding and capability, as most designs will start at this level and progress upward to synthesize the more complex circuits and systems of Table 1.1-2.

4.1 HOS SWITCH The switch finds many applications in integrated-circuit design. In analog circuits, the switch is used to implement such useful functions as the switched simulation of a resistor The switch is also useful for multiplexing, modulation, and a number of other applications. The

rt ].

113

114

ANALOG CMOS SUBCIRCUITS

Bluing Clmdh

~

Cumm SoGn:e

Cwren1 Mim1n

CUIRIIt

Sl.llk

llolm:c"

Cunont·

...._

Coupled 1'ait Mimlr Lood

Cunont·

S<~~m:o

Sink Lood F<>llo-

c.m.

Sint u

Figure 4.0-1 Dlustration of the hierarchy of analog circuits for an operational amplili<

switch is used as a transmission gate in digital circuits and adds a dimension of flexibility o found in standard logic circuits. The objective of this section is to study the characteristics switches that are compatible with CMOS integrated circuits. We begin with the characteristics of a voltage-controlled switch. Figure 4.1-1 shows model for such a device. The voltage lie controls the state of the switch-ON or OFF. 11 voltage-controlled switch is a three-terminal network with terminals A and B comprising ~ switch and terminal C providing the means of .applying the control voltage vc. The most il portant characteristics of a switch are its ON resistance, roN• and its OFF resistance, r0FP.Id ally, roN is zero and rOFF is infinite. Reality is such that roN is never zero and roFP is nev infinite. Moreover, these values are never constant with respect to tenninal conditions. In ge eral, switches can have some form of voltage offset. which is modeled by V0 s of Fig. 4.1· Vos represents the small voltage that may exist between terminals A and B when the .switch in the ON state and the cwrent is zero./0 w represents the leakage current that may flow in t OPF state of the switch. Cwrents / 14 and 18 represent leakage currents from the switch tern nals to ground (or some other supply potential). The polarities of the offset sources and lea age currents are not known and have arbitrarily been assigned the directions indicated in Fi 4.1-1. The parasitic capacitors are an important consideration in the application of anal• sampled-data circuits. Capacitors CA and C8 are the parasitic capacitors between the swit Figure 4.1-1 Model for a non-

law

ideal switch•

.---------~-.r---------~

•

A

I

t

4.1 MOS Switch

11 5

terminals A and Band ground. Capacitor C" 8 is the parasitic capacitor between the switch terminals A and B. Capacitors C,.c and C8 c are parasitic capacitors that may exist between the voltage-control terminal C and the switch terminals A and B. Capacitors C.o~c and Csc: contribute to the effect called charge feedthrough-wbere a portion of the control voltage appears at the switch terminals A and B. One advantage of MOS technology is that it provides a good switch. Figure 4.1-2 shows a MOS transistor that is to be used as a switch. Its performance can be determined by comparing Fig. 4.1-1 with the large-signal model for the MOS transistor. We see that either terminal, A or B, can be the drain or the source of the MOS transistor depending on the terminal voltages (e.g .• for ann-channel transistor, if terminal A is at a higher potential than B, then terminal A is the drain and terminal B is the source). The ON resistance consists of the series combination of ro. rs. and whatever channel resistance exists. Typically, by design, the contribution from r0 and r5 is small such that the primary consideration is the channel resistance. An expression for the channel resistance can be found as follows. In the ON state of the switch, the voltage across the switch should be small and v0 s should be large. Therefore, the MOS device is assumed to be in the nonsaturation region. Equation (3.1- I), repeated below, is used to model this state: (4.1-1)

where Vosis less than v05 - V7 butgreaterthan zero. (vru becomes v00 ifv05 is negative.)The small-signal channel resistance is given as roN=

1

I=

8i0 /ilvDS Q

L K'W(Vas- Vr- Yru)

(4.1-2)

where Q in Eq. (4.1-2) designates the quiesent point of the transistor. Figure 4.1-3 illustrates tbe drain current of an n-channel transistor as a function of the voltage across the drain and source terminals, plotted for equal increasing steps of Vas for WIL = 5/l. This figure illustnuea sdme very important principles about MOS transistor operation. Note that the curves are not symmetrical about V1 = 0. This is because the transistor terminals (drain and source) switch roles as V1 crosses 0 V. For example, when V 1 is positive, node B is the drain and node A is the source and V85 is fixed at -2.5 V and Vc;s is fixed as well (for a given Vc;). When V1 is negative, node B is the source and node A is the drain and as V1 continues to decrease, Vss decreases and Vc;s increases resulting in an increa...e in current. A plot of roN as a function of Vas is shown in Fig. 4.1-4 for Vas= 0.1 V and for W/L = l, 2, 5, and 10. It is seen that a lower value of roN is achieved for larger values of W!L. When Vas approaches V7 (V7 = 0.7 V in this case), roN approaches infinity because the switch is turning off.

c

A

1

Q>--.....3ni---O

Figure 4.1·1 An n-cbannel transistor used as a switch.

B

116

ANAJ..OC CMOS SUBCIRCUITS Figure 4.1·3 1-V cbaracteris\ic fl l'c:•SV

an n-channel tnmsistQr operating 11

).<J

1

V0 •4V

3:11

v.,.,Jv

2:J

i

a switch.

·v: ~2·V

10

2\Q

V6 •trlf·

lJ \\.5 it.ll

..o.s ..,\J.JJ

'<2,$.

Q,O V1 (YOIIS)

When Vell is less than or equal to V~ the sWitch is OFF and rOfll ill ideally infinite. Of course. it is never infinite, but because it is so large, the performance in the OPF stare fs dominated by the drain-bulk and source-bulk leakage cwrent as weU as subthreshold leakage from drain to source. The leakage from drain and source to bulk is primarily due to the pn. junction leakage current and is modeled in Pig. 4.1-1 as /A and /8 .'JYpically, this leakage corrent is on the order of l fAJj4tn1 ~room temperature and doubles for every .8 °C increase (see Example 2.5·1). The offset voltage modeled in Fig. 4.1-1 does not exist in MOS switches and thus is not a consideration in MOS switch performance. The capacitors C.t. c.., CAO and CK of Fig. 4.14

~~----------------------~

J

s

Flg11re 4.1-1 nlustration of ON resistance for liD n-channel transistor.

4.1

117

Figure 4.1·5 Application of an n-channel transistor as a switch with typical temtina.l voltages indicated.

OV • OI'P

SV·ON

(Dio 2V)

s

MOS Switch

D

Circuli 2

correspond directly to the capacitors CBS> C11 o. Cas. and Cao of the MOS transistor (see Fig. 3.2-1 ). CAll is small for the MOS transistor and is usually negligible. One important aspect of the switch is the range of voltages on the switch terminals cornpared to the control voltage. For the n-channel MOS transistor we see that the gate voltage must be considerably larger than either the drain or source voltage in order to ensure that the MOS transistor is ON. (For the p-channel transistor, the gate voltage mu.~t be considerably less than either the drain or source voltage.) 1Ypically, the bulk is taken to the most negative potential for the n-channel switch (positive for the p-channel switch). This requirement can be illustrated as follows for the n-channel switch. Suppose that the ON voltage of the gate is the positive power supply VDD· With the bulk to ground this should keep then-channel switch ON until the signal on the switch terminals (which should be approximately identical at the source and drain) approaches VDD - Vr· As the signal approaches V00 - Vr the switch begins to turn OFF. Typical voltages used for an n-channel switch are shown in Fig. 4.1-5, where the switch is connected between the two networks shown. Consider the use of a switch to charge a capacitor as shown in Fig. 4.1-6. Ann-channel transistor is used a.~ a switch and V~ is the control voltage (clock) applied to the gate. The ON resistance of the switch is important during the charge transfer phase of this circuit. For example, when goes high (V,. > Vtn + Vr). Ml connects C to the voltage source via. The equivalent circuit at this time is shown in Fig. 4.1-7. It can be seen that C will charge to V;, with the time constant of roNC. For successful operation r 0111 C << T. where Tis the time Vo~ · · · is high. Clearly, roN varies greatly with Vas. as illustrated in Fig. 4.1-4. The worst-case value for roN (the highest value). during the charging of C. is when VDs = 0 and Vas = Vo~ - v1". This value should be used when sizing the transistor to achieve the desired charging time. Consider a case where the time V,. is high is T = 0.1 J.tS and C = 0.2 pF; then row must be less than 100 ill if sufficient charge transfer occurs in five time constants. For a 5 V clock

v,.

Figure 4.1-6 An application ofa MOS switch.

118


Flgure4.1-7 Model for the ON state of the switehin Fig. 4.1-6.

swing and vu, of 2.5 V, the MOS device of Fig. 4.1-4 with W = L gives roN of approximately 6.4 k!l, which is sufficiently small to transfer the charge in the desired time. It is der.irable to keep the switch size as small as possible (minimize W X L) to minimize charge feedthrougb from the gate. The OFF state of the switch has little influence on the perfonnance of the circuit in Fig. 4.1-6 except for the leakage current. Figure 4.1-8 shows a sample-and-hold circuit where the leakage current can create serious problems. If Cn is not large enough, then in the hold mode where the MOS switch is OFF the leakage current can charge or discharge CH a significant amount. One of the most serious limitations of monolithic switches is the clock feedthrou,gh effect. Clock feedthrough (also called charge injection and charge feedthrough) is due to the coupling capacitance from the gate to both source and drain. This coupling allows charge to be transferred from the gate signal (which is generally a clock) to the drain and source nodes-an undesirable but unavoidable effect. Charge injection involves a complex process whose resulting effects depend on a number of factors such as the layout of the transistor, its dimension~. impedance levels at the source and drain nodes, and gate waveform. It is hopeless to attempt to describe all of these effects precisely analytically-we have com· puters to do that! Nevertheless, it is useful to develop a qualitative understanding of this imponant effect. Consider a simple circuit suitable for studying charge injection analysis as shown in ·Fig. 4.1-9(a). Figure 4.1-9(b) illustrates modeling a transistor with the channel symbolized as a resistor, Rcnan•cl• and gate-channel coupling capacitance denoted Cchannel· The values of C.......,.,1 and R,han.,.,1 depend on the terminal conditions of the device. The gate~channel cou· piing is distributed across the channel as is the channel resistance, Rwnnol· In addition to the channel capacitance.. there is the overlap capacitance, CGSO and CGDO. It is convenient to approximate the total channel capacitance by splitting it into two capacitors of ~ual size placed at the gate-source and gate-drain terminals as illustrated in Fig. 4.1-9(c).

1

Figure 4.1-8 Example of !he inftuence of low in a sample-and-hold circuiL

4.1

MOS Switch

119

••

1 +

"ct.

{b)

(c)

Figure 4.1-9 (a) Simple switch circuit useful for studying charge injection. (h) Distributed model for the transistor switch. (c) Lumped model of Fig. 4.1-9(a).

For the circuit in Fig. 4.1-9, charge injection is of interest during a high-to-low transition at the gate of IP 1• Moreover, it is convenient to consider two cases regarding the gate transitiona fast transition time and a slow transition time. Consider the slow transition case first (what is meant by slow and fast will be covered shortly). As the gate is falling, some charge is being injected into the channel. However, initially, the transistor remains on so that whatever charge is injected flows in the input voltage source, Vs. None of this charge will appear on the load capacitor, CL. As the gate voltage falls, at some point. the transistor turns off (when the gate volt· age reaches Vs + VT). When the transistor turns off, there is no other path for the injected charge other than into CL. For the fast case, the time constant associated with the channel resistance and the channel capacitance limits the amount of charge that can flow to the source voltage so that some of the channel charge that is injected while the transistor is on conmbutes to the total charge on CL. To develop some intuition about the fast and slow cases, it is useful to model the gate voltage as a piecewise constant waveform (a quantized waveform) and consider the charge flow at each transition as illustrated in Fig. 4.1-10. ln this figure, the range of voltage at the CL illustrated represents the period while the transistor is on. In both cases, the quantized voltage step is the same, but the time between steps is different. The voltage across CL is observed to be an exponential whose time constant is due to the channel resistance and channel capacitance and does not change from the fast case to the s]ow case.

120


Flgut'll4.1·10 DluSI!'IItion of (a) slow ramp and (b) fast ramp using a quantized vollage ramp to illustrate !he effects due to the time constant of the channel resistance ·and c:apac:itanc:e. Vol•

Time (b)

Analytical expressions have been derived that describe the approximate operation of a tnms.istor in the slow and fast regimes l2J. Consider the gate voltage traVeRing from VH to VL (e.g., 5.0 V to 0.0 V, respectively} described in the time domain as (4.1-3) where U is the magnitude of the slope of vc;(t), When operating in the slow regime defined by the relationship (4.1-4) where VHT is defined as (4.1-S) the error (the difference between the desired voltage Vs and the actual voltage Vc) due to charge injection can be described as

Vmur = (W · CGDO

+ ~)

c~.

r;uc;_ + W · CGDO
'\fu

cL

VL)

(4.1-6)

4.1 MOS Switch

121

In the fast switching regime defined by the relationship

(W~

«

U

(4.1-7)

2C.L the error voltage is given as

Cchan.,.l)

W' CGDO + - 2 V.,.,..,..= (

CL

f3VJn.

(vHT- 6UCJ +

W · CGOO CL

(Vs+ Vr- ViJ (4.1-8)

The following example illustrates the application of the charge feedthrough model given by Eqs. (4.1-3) through (4.18).

CALCULATION OF CHARGE FEEDTHROUCH ERROR

=

Calculate the effect of charge feedthrough on the circuit shown in Fig. 4.1-9, where Vs 1.0 V, CL = 200 fF, WIL = 0.8 j.i.m/0.8 ~m. and Vcis given for two cases illustrated below. Use model parameters from Tables 3.1-2 and 3.2-1. Neglect ~Land ~Weffects.

0.2ns

t - - - - - t o .. - - -.... Timo

lfJM!t.t,l Ccue 1: The first step is to detennine the value of U in the expression

For a transition from 5 V to 0 V in 0.2 ns, U = 25 X 109 VIs. In order to determine operating regime, the following relationship must be tested:

,svb CL 2

>>

U for slow

or

,svb C£ 2

<<

U for fast

122


Observing that there is a backbias on the transistor switch affecting V11 VHT is

Vm

= V8

-

Vs - Vr = 5 - 1 - 0.887

= 3.113

giving

~v~ 2CL

-- =

110 x to- 6 x 3.1132 = 2.66 X 109 2 X 200 X 10- 1 ~

<<

25 X 109

thus fast regime

Applying Eq. ( 4.1-8) for the fast regime yields

v.

ermr

176 = (

xw-~· +

1.58

200 X 10

~ to-u) (

xto-3)

3.32 3 113 - .;...;..:..;:,_..:...;;..:• 30 X 10-3 176 X 10-11 + 200 x w-•5 {5

15

+ o.ss7- O)

V...,. = 19.7mV

Case 2: The first step is to determine the value of U in the expression

For a transition from 5 V to 0 V in 10 ns, U = 5 X l
V: enur

=

176 X 10-18 (

+ 1.ss x2

200 X 10-1!1

w-•')

(314 X 10-fi)l/2

220 X 10- 6

+

176 X 10-18 (5

200 x

w-u

+ 0.887- 0)

V.....,.= 10.95mV This example illustrates the application of the charge feedthrough model. The reader should be cautioned not to expect Eqs. (4.1-3) through (4.1-8) to give precise answers regarding the amount of charge feedthrough one should expect in an actual circuit. The model should be used as a guide in understanding the effects of various circuit elements and tenninal conditions in order to minimize unwanted behavior by design. It is possible to partially cancel some of the feedthrough effects using the technique illustrated in Fig. 4.1-11. Here a dummy MOS transistor MD (with source and drain both attached to the signal line and the gate attached to the inverse clock) is used to apply an opposing clock feedthrough due to Ml. The area of MD can be designed to provide minimum clock feedthrough. Unfortunately, this method never completely removes the feedthrough

4.1 MOS Switch

123

Figure 4.1-11 The use of a dummy uansistor 10 cancel clock feedthrough.

Ml

MD

and in some cases may worsen it. Also, it is necessary to generate an inverted clock, which is applied to the dummy switch. Clock feedthrough can be reduced by using the largest capacitors possible, using minimum-geometry switches, and keeping the clock swings as small as possible. 1)1pically, these solutions will create problems in other areas, requiring some compromises. The dynamic range limitations associated with single-channel MOS switches can be avoided with the CMOS switch shown in Fig. 4.1-12. Using CMOS technology, a switch is usually constructed by connecting p-channel and n-channel enhancement transistors in parallel as illustrated. For this configuration, when 1/1 is low, both transistors are off. creating an effective open circuit When 1/1 is high, both transistors are on, giving a low-impedance state. The bulk potentials of the p-channel and the n-channel devices are taken to the high~ est and lowest potentials, respectively. The primary advantage of the CMOS switch over the single-channel MOS switch is that the dynamic analog-signal range in the ON state is greatly increased. The increased dynamic range of the analog signal is evident in Fig. 4.1- I 3, where the on resistance of a CMOS switch is plotted as a function of the input voltage. In this figure, the p-channel and n-cbannel devices are sized in such a way that they have equivalent resistance with identical terminal conditions. The double-peak behavior is due to the n-channel device dominating when V;n is low and the p-channel dominating when V;0 is high (near V00). At the midrange (near V0 of2), the parallel combination of the two devices results in a minimum. The dip at midrange is due to mobility degradation effects and is not evident when analyzed using the LEVEL 1 model. In this section we have seen that MOS transistors make one of the best switch realizations available in integrated-circuit form. They require small area, dissipate very little power, and provide reasonable values of roN and r0 pp for most applications. The inclusion of a good realization of a switch into the designer's basic building blocks will produce some interesting and useful circuits and systems that will be studied in the following chapters. Figure 4.1-12 A CMOS switch.

A

8

24

ANAlOG CMOS SUBCIRCUITS

3.S , - - - - - - - - - - - - - - - - - ,

Flgure4.1-13 roN ofFig4.J-12 as a function of the voltage v..

I.S 0.0

v., (volts) '.2 HOS DIODE/HCTIYE RESISTOR When tbe gate and drain of an MOS ttansistor are tied together as illustrated in Figs. 4.2- I(a) and 4.2-l(b), tbe 1-V characteristics are qualitatively similar to a pn-junction diode, thus the name MOS diode. The MOS diode is U8ed as a component of a current mirror (Section 4.4) and for level translation (voltage drop).

I

I~ (a)

(b)

v (C)

(d)

Figure 4.2·1 Active re.o;istor. (a) n-CbanneL. (b) p-ChB.Illlel. (c) 1-V characteristics for n-cbannel case. {d) Small-signal model.

4.2 MOS Diode/Active Resistor

125

The I-V characteristics of the MOS diode are illustrated in Fig. 4.2-l(c) and described by the large-signal equation for drain current in saturation (the connection of the gate to the drain guarantees operation in the saturation region) shown below. I= ID =

K'W) ((Vas (2L

Vr) 21 =

213 (Vas -

Vr) 2

(4.2-1)

or

V= Vas= Vos= Vr+ ~

(4.2-2)

If V or I is given, then the remaining variable can be designed using either Eq. (4.2-1) or Eq.

(4.2-2) and solving for the value of /3. Connecting the gate to the drain means that v05 controls i0 and therefore the channel transconductance becomes a channel conductance. The small-signal model of an MOS diode (excluding capacitors) is shown in Fig. 4.2-l(d). It is easily seen that the small-signal resistance of an MOS diode is

1

Tout=

8m

+ Cm~>< + gdt

1 Cm

a&-

(4.2-3)

where g, is greater than Km111 or Kds• An illustration of the application of the MOS diode is shown in Fig. 4.2-2, where a bias voltage is generated with respect to ground (the value of such a circuit will become obvious later). Noting that VDS = Vas for both devices, (4.2-4) VoiAS

v,,

= Vosl + VDS1 =

2VoN

+ 2Vr

Figure 4.2-l Voltage division using active resistors.

(4.2-5)

126

ANALOG CMOS SUSCIRCUITS Figure 4.2-3 Floating active resistor usiog a single MOS ttansisiOr.

The MOS switch described in Section 4.1 and illustrated in Fig. 4.1-2 can be viewed as a resistor. albeit rather nonlinear as illustrated in Fig. 4.1-4. The nonlinearity can be mitigated where the drain and source voltages vary over a small range so that the transistor ON resistance can be approximated as small-signal resistance. Figure 4.2-3 illustrates this point showing a configuration where the transistor's drain and source form the two ends of a "floating" resistor. For the small-signal premise to be valid, v00 is assumed small. The 1-V characteristics of the floating resistor are given by Fig. 4.1-3. Consequently, the range of resistance values is large but nonlinear. When the transistor is operated in the nonsaturation region, the resistance can be calcuLated from Eq. (4.1-2), repeated below, where Vos is assumed small.

L r•=-----K'W
(4.2-6)

CALCULATION OF THE RESISTANCE OF AN ACTIVE RESISTOR The floating active resistor of Fig. 4.2-3 is to be used to design a I k!l resistance. The de value of VAJI = 2 V. Use the device parameters in Table 3.1-2 and assume the active resistor is an n-channel transistor with the gate voltage at 5 V. Assume that Vos = 0.0. Calculate therequired WIL to achieve 1 k!l resistance. The bulk terminal is 0.0 V.

Before applying Eq. (4.2-6), it is necessary to calculate the new thre.~hold voltage, Vl\ due to v~~.~ not being zero (IV11sl = 2 V), From Eq. {3.1-2) the new Vr is found to be 1.022 V. Equating Eq. (4.2·6) to 1000 !l gives a WIL of 4.597 = 4.6.

4.3

CURRENT SINHS HID SOURCES A current sink and current source are two terminal components whose current at any instant of time is independent of the voltage across their terminals. The current of a current sink or source flows from the positive node. through the sink or source, to the negative node. A current sink typically has the negative node at Vss and the current source bas the positive node at VDo• Figure 4.3-l(a) sbows the MOS implementation of a current sink. The gate is taken to whatever voltage is necessary to create the desired value of current. The voltage divider of Fig. 4.2-2 can be used to provide this voltage. We note that in the nonsaturation region the MOS

4.3 Current Sinks and Sources

127

Figure 4.3-l (a) Cum:nt sink. (b) Cum:nt-voltage cbaracteristk:s of (a),

(b)

(a)

device is not a good current source. In fact, the voltage across the current sink must be larger than VMIN in order for the current sink to perform properly. For Fig. 4.3-l(a) this means that (4.3-l)

If the gate-source voltage is held constant, then the large-signal characteristics of the MOS transistor are given by the output characteristics of Fig. 3.1-3. An example is shown in Fig. 4,3-1 (b}. If the source and bulk are both connected to ground. then the small-signal output resistance is given by [see Eq. (3.3-9)] r-=

1 + XVos )JI)

1 ""'-

(4.3-2)

)JD

If the source and bulk are not connected to the same potential, the characteristics wiD not change as long as Vss is a constant. Figure 4.3-2(a) shows an implementation of a current source using a p-channel transistor. Again, the gate is taken to a constant potential as is the source. With the definition of v00T and ioUT of the source as shown in Fig. 4.3-2(a}, the large-signai/-V characteristic is shown in Fig. 4.3-2(b). The small-signal output resistance of the current source is given by Eq. (4.3-2). The source-drain voltage must be larger than VMlN for this current source to work properly. This current source only works for values of v0 UT given by Votrr :S

Voa

+ IVrol

(4.3-3)

Flgllft 4.3-2 (a) Cum:nt 50utce. (b) Current-voltage cbaracterisrics of{a).

~

(a)

(b)

128


The advantage of the current sink and source of Figs. 4.3-l(a) and 4.3-2(a) is their simplicity. However, there are two areas in which their performance may need to be improved for certain applications. One improvement is to increase the small-signal output resistance-resulting in a more constant current over the range of VoUT values. The second is to reduce the value of VMTN, thus allowing a larger range of VoUT over which the current sink/source works properly. We shall illustrate methods to improve both areas of performance. First, the small-signal output resistance can be increased using the principle illustrated in Fig. 4.3-3(a). This principle uses the common-gate configuration to multiply the source resistance r by the approximate voltage gain of the common-gate configuration with an infinite load resistance. The exact small-signal output resistance r0111 can be calculated from the small-signal model of Fig. 43-3(b) as (4.3-4) where g,. 2r.u2 >> 1 and gm2 > gmiH2· The above principle is implemented in Fig. 4.3-4(a), where the output resistance (rc~s 1 ) of the current sink of Fig. 4.3-1 (a) should be increased by the common-gate voltage gain of M2. To the principle, the small-signal output resistance of the cascode current sink of Fig. 4.3-4(a) will be calculated using the model of Fig. 4.3-4(b). Since vg.a == -v1 and v1 , 1 = 0, summing the currents at the output node gives (4.3-5) Since v1 = i0111 rdt1> we can solve for rout as (4.3-6)

'JYpically, gm2rc1s2 is greater than unity so tbst Eq. (4.3-6) simplifies to (4.3-7)

-

iOUT

+

.... (a)

(b)

Figure 4.3-3 {a) Technique for increasing the output resistance of a tellistor r. (b) Smallsignal model for tbe circuit in (a).


129

.....

10\fl'

+

+

M2

Vc;c

O---f

L-our

Vc:c

0-----1

+

Ml

(b)

(a)

Figure 4.3-4 (a) Circuit for inc:reasing rom of a current sink. (b) Small-signal model for the circuit in (a).

We see that the small-signal outpUt resistance of the current sink of Fig. 4.3-4(a) is increased by the factor of 8m2rtk2•

CALCUlATION OF OUTPUT RESISTANCE FOR A

CURRENT SINK Use the model parametel'8 of Table 3.1-2 to .calculate: (a) the small-signal output resistance for the simple current sink of Fig. 4.3-l(a) if loUT= 100 JJ.A; and (b) the small-signal output resistance if the simple current sink of (a) is inserted into the cascode current-sink configuration of Fig. 4.3-4(a). Assume that W11L1 = W21Lz = I. Solution (a) Using}.. = 0.04 and /OOT = 100 IJ.A gives a small-signal output resistance of 250 kO. (b) The body-effect tenn, Rmb.a· can be ignored with little error in the result Equation (3.3-6) gives 8ml = gm2 = 148JJ.A/V. Substituting these values into Eq. (4.3-7) gives the small-signal output resistance of the cascade current sink a'l 9.25 MO.

The other performance limitation of the simple current sink/source was the fact that the constant output current could not be obtained for all values of vOUT. This was illustrated in Figs. 4.3-l(b) and 4.3-2(b). While this problem may not be serious in me simple current sink/source, it becomes more severe in the cascode current-sink/source configuration that was used to increase the small-signal output resistance. It therefore becomes necessary to examine methods of reducing the value of VMTN [3]. Obviously, VMIN can be reduced by increasing the value of WIL and adjusting the gate-source voltage to get the same output current. However, another method that works well for the cascode current-sink/source configuration will be presented. We must introduce an important principle used in biasing MOS devices before showing the method of reducing VMJN of me cascade current sink/source. This principle can best be

130


illustrated by considering two MOS devices, Ml and M2. Assume that the applied de gate-source voltage VGS can be divided into two parts, given as

(4.3-8) where V0 ,. is that part of VGS which is in excess of the threshold voltage, Vr. This definitionallows us to express the minimum value of v05 for which the device will remain in saturation liB

vos(sat)

= Vas-

Vr

= VON

(4.3-9)

Thus, VoN can be thought of as the minimum drain-source voltage for which the device n:mains saturated. ln saturation, the drain current can be written as (4.3-lO) The principle to be illustrated is based on Eq. (4.3-10). If the currents of two MOS devices are equal (because they are in series). then the following relationship holds: (4.3-11)

If both MOS transistors are of the same type, then Eq. (4.3-11} reduces to (4.3-12)

or

(4.3-13)

The principle above can also be used to define a relationship between the current and WIL ratios. If the gate-source voltages of two similar MOS devices are equal (because they are physically connected), then VoN! is equal to Yom· From Eq. (4.3-10) we can write (4.3-14) Equation ( 4.3-13) is useful even tllough the gare-source tenninals of M I and M2 may not

be physically connected because voltages can be identical without being physically connected, as will be seen in later material. Equations (4.3-13) and (4.3-14) represent a very important principle that will be used not only in the material immediately following but throughout this text to determine biasing relationships.

4.3 Current Sinks and Sour\:es

131

Consider the cascode CUI'l'ent sink of Fig. 4.3-S(a). Our objective is to use the above principle to reduce rhe value of VMIN•Ifwe ignore the bulk eff«ts oo M21Hld M4 and usume tha.t Ml. M2, M3, and M4 are aJI matched with identical WIL ratios, then the gate-source voltage of each transistor can be expressed as Vr + VoN as shown in Fig. 4.3-S(a). At the gate of M2 we see that the voltage with respect to the lower power supply is 2Vr + 2VoN· In order to maintain current-sink/source operation, it will be assumed that Ml and M2 must have at least a voltage of VON as given in Eq. (4.3-9). In order to find VllflN of Fig. 4.3-S(a) we can rewrite Eq. (3.1-15) as

(4.3-15) Since V02 = 2Vr+ 2 V0 .v. substituting this va1ue into Eq. (4.3-15) gives Vm(min} =

= Vr

VMIN

+ 2VoN

The current-voltage characteristics of Fig. 4.3-5(a) are illustrated in Fig. 4.3-5(b), where the value of VMIN ofEq. (4.3-16) is shown. VMIN of Eq. (4.3-16) is dropped across both Ml and M2. The drop across M2 is VoN while the drop across Ml is Vr +VoN· From the results ofEq. (4.3-9), this implies that VMIN of Fig. 4.3-5 could be reduced by Vr and still keep both Ml and M2 in saturation. Figure 4.3-6(a) shows how this can be accomplished [4]. The WIL ratio ofM4 is made one-quarter of the identical WIL ratios of Ml through M3. This causes the gate-source voltage across M4 to be Vr + 2 VaN rather than V1 + VoN· Consequently, the voltage at the gate of M2 is now V1 + 2 VoN· Substituting this value into Eq. (4.3-15) gives V02 (min) = VMIN = 2 VoN

(4.3-17)

The resulting cwrent-voltage relationship is shown in Pig. 4.3-6(b). It can be seen that a vo1tage of2 V0Nis across both Ml and M2, giving the lowest value of VMIN and still keeping both M l and M2 in saturation. Using this approach and increasing the W/L ratios will result in minimum values of VMIN,

v_

lovr-

..L.

..i.'-------

0 (b) Cal Figure 4.3-5 (a) Standard cascode current sink. (b) Output characteristics of ciJt:uit in (a).

132

ANAlOG CMOS SUBCIRCUITS

+

______

io\IT

Va

.L.;•.

0

2VON

(a)

(b)

Figure 4.3-6 (a) High-swing cascode. (b) Output characteristics of circuit in (a}.

DEG THE CASCODE CURRENT SINK FOR A GIVEN VMIN Use the ca<>eode current-sink configuration of Fig. 4.3-6(a) to design a clliTCnt sink of I00 JAA and a VMJN of 1 V. Assume the device parameters of Table 3.1-2.

IJ!1Mh.J.i With V.'-11.-; of 1 V. choose V0 ,., through M3 can he found from

W

= O.S V.

2 iotJT

""i = x·vJ,...

Using the saturation model, the WIL ratio of Ml

2 X 100 X 10-6 6 x o.25 = 110 x

w-

= 7 '27

The W/L ratio of M4 will be one-quarter this value or 1.82, A problem exists with the circuit i11 Fig. 4.3-6. The V/)5 of Ml and the Vos of M3 are not equal. Therefore, the current iouT will not be an accurate replica of /REF due to channel length modulation as well as drain-induced threshold shift. If precise mirroring of the current /REF to loUT is desired, a sUght modification of the circuit of Fig. 4.3-6 will minimize this problem. Figure 4.3-7 illustrates this fix. An additional transistor, MS. is added in series with M3 so as to force the drain voltages of M3 and Ml to be equal, thus eliminating any errors due to channel length modulation and drain-induced threshold shift. The above technique will be useful in maximizing the voltage-signal swings of cascode configurations to be studied later. This section ha.~ presented implementations of the current sink/source and has shown how to boost the output resistance of a MOS device. A very important principle that will be used in biasing was based on relationships between the excess gate-source voltage VoM the drain current, IIIld the WIL ratios of MOS devices. This principle was applied to reduce the voltage VMII'f of the cascade current sou~e. When power dissipation must be kept at a minimum. the circuit in Fig. 4.3-7 can be modified to eUminate one of the /11.EP currents. Figure 4.3-8 illustrates a self-biased cascode current source that requires only one reference current [5j.


133

Figure 4.3-7 Improved high-swing cascade.

DEG THE SELF-BIASED HIGH-SWING CASCODE CURRENT SINK FOR A GIVEN VMIN Use the cascode current-sink configuration of Fig. 4.3-8 to design a current sink of 250 p.A and a VMIN of 0.5 V. Assume lhe device parameters of Table 3.1-2.

l't'MU.I,I With VMIN of 0.5 V, choose VoN= 0.25 V. Using the saturation mode], the WIL ratio ofMI and M3 can be found from 2 X 500 X 10- 6 "="72.73 K'V~N - 110 X 10 6 X 0.0626

W 2 ioUT -=--L

Figure 4.3-8 Self-biased high-swing cascode current .source.

134

ANALOG CMOS SUBCIRCUJTS The back-gate bias on M2 and M4 is -0.25 V. Therefore, the threshold voltage for M2 and M4 is calculated to be VTH = 0.7

+ 0.4 ( Y0.25 + 0.7-

'\!"o.?) = 0.755

Thking into the increased value of the threshold voltage, the gate voltage of M4 and M2is VGol

= 0.755 + 0.25 + 0.25 = 1.255

The gate voltage of Ml and M3 is Va 1 = 0.70

+ 0.25

= 0.95

Both tenninals of the resistor are now defined so that the required resistance value is easily calculated to be R = VG4- VGI 250 X 10 6

4.4

= 1.255- 0.95 = 12200 250 X 10- 6

CURRENT MIRRORS Cum:nt mirrors are simply an extension of the current sink/source of the previous section. In fact. it is unlikely that one would ever build a current sink/source that was not biased as a current mirror. The current mirror uses the principle that if the gate-source potentials of two identical MOS transistors are equal, the channel currents should be equal. Figure 4.4-1 shows the implementation of a simple n-channel current mirror. The current i 1 is assumed to be delined by a current source or some other means and i0 is the output or ''mirrored" current. Ml is in saturation because llvs 1 = Vas•· Assuming that Vvsz ~Von- Vn is greater than Vn al· lows us to use the equations in the saturation region of the MOS transistor. In the most general case, the ratio of i0 to i1 is (4.4-1)

Figure 4.4-1 a-Channel cuneut mirror.

+ VDSl

4.4 Current Mirrors

135

Normally. the components of a current mirror are processed on the same integrated circuit and thus all of the physical parameters such as Vrand K' are identical for both devices. As a result, Eq. (4.4-J) simplifies ro (4.4-2)

If vm2 =

VDSt

(not always a good assumption}, then the ratio of i0 /i1 becomes (4.4-3)

Consequently, i0 1i1 is a function of the aspect ratios that are under the control of the designer. There Bte three effects that cause the currem mi"or to be rl}Jferenf from the jdeat situation ofEq. (4.4-3). These effects are (1) channel length modulation, (2) threshold offset between the two transistors, and (3) imperfect geometrical matching. Each of these effects will be analyzed separately. Consider the channel length modulation effect. Assuming all other aspects of the transistor are ideal and the aspect ratios of the two transistors are both unity, then Eq. (4.4-2} simplifiesto

io 1 + AVDJl -=--=

(4.4-4)

with the assumption that X is the same for both transistors. This equation shows that differences in drain-source voltages of the two transistors can cause a deviation from the ideal unity current gain or current mirroring. Figure 4.4-2 shows a plot of current ratio error versus Figure 4.4-Z Plot of ratio error (io %) versus drain volr.age difference for the current mirror of Fig. 4.4-1. For this plot. vru1 = 2.0 V.

8.0

...

7.0

"

6.0

~

,......------,

;o~ ;oa

"'+ "'+ ..............

J

!

5.0 4.0

3.0 2.0

1.0 0.0 0.0

1.0

l.O

3.0

4.0

s.o

136

ANALOG CMOS SUBCIRCUITS vDS2 - vvs 1 for different values of >.. with both tran~ .. becomes smaller (output resistance becomes larger). Thus, a good current mirror or current amplifier should have identical drain-source voltages and a high output resistance. The second nonideal effect is that of offset between the threshold voltage of the two tran· sistors, For clean silicon-gate CMOS processes, the threshold offset is typically less than I 0 mV for transistors that are identical and in close proximity to one another. Consider two transistors in a mirror configuration where both have the same drain-source voltage and all other aspects of the transistors are identical except V7 . In this case, Eq. (4.4-1) simplifies to

i~ = (Vos -

Vn)

1

(4.4-5)

Vos- Vn

lt

Figure 4.4-3 shows a plot of the ratio error versus AVn where AV7 = VTI - Vn. It is obvious from this graph that better current-mirror performance is obtained at higher currents, because Vas is higher for higher currents and thus AV7 becomes a smaller percentage of Vos· It is also possible that the transconductance gain K' of the current mirror is also mismatched (due to oxide gradients). A quantitative analysis approach to vllliations in both K' and V7 is now given. Let us assume that the WIL ratios of the two mirror devices are exactly equal but that K' and V7 may be mismatched. Equation (4.4-5) can be rewritten as

io Ki (vas - Vn)2 -= Kj (vas- Yn):z il

Flgut'e 4.4-3 Plot of ratio error (in%) versus offset voltage for the current mirror of Fig. 4.4-1. For this plot, Vn = 0.7 V and 2 K'WIL = ll0~ •

16.0 1-4.0

Ill

§

I :!.II

~

..---. I

10.0

-=1·-- 8.0 ...............

I j

(4.4-6)

~.0

4.0 l.O

0.0 0.0

1.0

2.0

3.0

4.1)

5.0

6.Cl

AV7 CmV)

7.0

a.o

9.0

10

4.4 Current Mirrors

137

where vas 1 = v051 = Vc;s. Defining M' = K~ - K\ and K' = 0.5(K~ + KD and AVr = VnVn and Vr= 0.5(Vn + Vn) gives

= K' -

O.SM'

(4.4-7)

K2 = K' + 0.5M'

(4.4-8)

Vn = Vr- O.SAVr

(4.4-9)

+ O.SAVr

(4.4-10)

Kj

Vn = Vr

Substituting Eqs. (4.4-7) through (4.4-10) into Eq. (4.4-6) gives

io

(K'

+ 0.5AK')(vc;s- Vr- 0.5AVr)2

- '"'" ~-----'-'-~--'------=-=-=2 i1 (K' - O.SAK')(vc;s- Vr + 0.5AVr)

(4.4-11)

Factoring out K' and (vas- V7) gives

( M')(

2

AVr ) 1+- 1---.!.....--io 2K 2(Vas- Vr) - "" -:------:---o-_....:....::::::___.:..:.:-""'1

ir

(4.4-12)

( l - -AK') ( 1 + . ---'--AVr ) 2K

2(Vcs - Vr)

Assuming that the quantities in Eq. (4.4-12) following the "1" are small. Eq. (4.4-12) can be approx.imall:d as

AK') (t +AK' AVr ) (t -----=---AVr ) - ) (12K' 2(vas - Vr) · 2(vas - Vr) 2

ioa ; ;,

( 1+2K'

2

(4.4-13}

Retaining only first-order products gives io M<' - a 1 +-i1 K'

2AVr ---.:....Vc;s-

Vr

(4.4-14)

If the percentage change of K' and Vr are known. Eq. (4.4-14) can be used on a worst-case basis to predict the error in me current-mirror gain. For example, assume that M'IK' = ±5% and AVrl(vas- V7 ) = :!:10%. Then the current-mirror gain would be given as i0 /iJ a I ±. 0.05 ±. (-0.20) or I ±. ( -0.15) amounting to a 15% error in gain assuming the tolerances of K' and Vr are correlated. The third nonideal effect of current mirrors is the error in the aspect ratio of the two devices. We saw in Chapter 3 that there are differences in the drawn values of Wand L. These are due to mask, photolithographic, etch, and outdiffusion variations. These variations can be different even for two transistors placed side by side. One way to avoid the effects of these variations is to make the dimensions of the transistors much larger than the typical variation one might see. For transistors of identical size with Wand L greater than 10 Jl.m, the errors due to geometrical mismatch will generally be insignificant compared to offset-voltage and vo.rinduced errors.

138


In some applications, the current mirror is used to multiply current and function as a current amplifier. In this case, the aspect ratio of the multiplier transistor (M2) is much greater than the aspect ratio of the reference uansistor (Ml). To obtain the best performance, the geometrical aspects must be considered. An example will illustrate this concept. ASPECT RATIO ERRORS IN CURRENT AMPLIFIERS Figure 4.4-4 shows tbe layout of a one-to-four current amplifier. Assume that the lengths are identical (LI = LiJ and find the ratio error if WI = 5 :t 0.05 j.l.m and w2 = 20 ± 0.05 j.l.m.

Figure 4.4-4 Layout of cum:nt mirror wilhout aW correctioo.

The actual widths of the two transistors are

Wt = 5 ± 0.05

j.l.ffi

and

w:2 =

20 ±

o.o5 jUII

We note that the tolerance is not multiplied by the nominal gain factor of 4. The ratio of W2 to W1 and consequently the gain of the current amplifier is

io = w2 it WI

= 20 + 0.05 == 4 5

± 0.06

+ 0 05

-

.

where we have assumed that the variations would both have the same sign. It is seen that this ratio error is 1.25% of the desired cum:nt ratio or gain. The error noted above would be valid if every other aspect of the transistor were matched perfectly. A solution to this problem can be achieved by using proper layout techniques. The correct one-to-four ratio should be implemented using four duplicates of the transistor M 1. In this way, the tolerance on W2 is multiplied by the nominal current gain. Let us reconsider the above example using this approach.

<4.4 Current Mirrors

139

REDUCTION OF THE ASPECT RATIO ERROR IN CURRENT AMPLIFIERS Use the layout technique illustrated in Fig. 4.4-5 and calculate the ratio error of a current amplifier having the specifications of the previous example.

II

!I ''I

I

-

I ;c; • ~'"' ; ·""; • .-R • • ·,"''"' • • 1'""'"'-. ! ·h'" .: -~ : !. ~- ~ "" ·'""""' M2o

"•"

"""- Mlb

Ml 1 ~:'Ji·

IIUc

';' "'-,

'---

OND

1-.. 1

•

"•

•

f\•

Figure 4.4-5 Layout of cuacnt mirror with AW correction as weD as common-centroid layout techniques.

lfiMit.t.i The actual widths ofMl and M2 are

w.=s±o.os . . m and W2 = 4(5 The ratio of W2 to

~ 0.05)

p.m

W1 and consequently the current gain is seen to be i0 = 4(5 ± 0.05) = 4 5 ± 0.05 it

In the above examples we made the assumption that 1!. W should be the same for all transistors. Unfortunately, this is not true, but the 1!. W matching errors will be small compared to the other error contributions. If the widths of two transistors are equal but the lengths differ, the scaling approach discussed above for the width is also applicable to the length. Usually one does not try to scale the length because the tolerances are greater than the width tolerances due to diffusion (outdiffusion) under the polysilicon gate. We have seen that the small-signal output resistance is a good measure of the perfection of the current mirror or amplifier. The output resistance of the simple n-channel mirror of Fig. 4.4-1 is given as (4.4-15)

140

ANALOG CMOS SUBCIRCUITS Figure 4.4-6 Standard cascade current sink.

M3

1\114

Ml

M2

Higher-performance current mirrors will attempt to increase the value of r...,. Equation (4.4-15) will be the point of comparison. Up to this point we have discussed aspects of and improvements on the current mirror or current amplifier shown in Fig. 4.4-l, but there are ways of improving current-mirror performance using the same principles employed in Section 4.3. The current mirror shown in Fig. 4.4-6 applies the cascode technique, which reduces ratio errors due to differences in output and input voltages. Figure4.4· 7 shows an equivalent small-signal model of Fig. 4.4-6, To find the small-signal output resistance, set i1 = 0. This causes the small-signal voltages v1 and v3 to be zero. Therefore, Fig. 4.4-7 is exactly equivalent to the circuit of Example 4.3-1. Using the correct sulr scripts for Fig. 4.4-7, we can use the results ofEq. (4.3-6) to write (4.4-16) We have already seen from Example 4.3-1 that the small-signal output resistance of this configuration is much larger than for the simple mirror of Eq. (4.4-15). Another current mirror is shown in Fig. 4.4-8. This circuit is an n-chAnnel implementa· lion of the well-known Wilson current mirror [6]. The output resistance of the Wilson current

04

+ v)

I"

+-+

+

.4

•

0

Figure 4.4-7 Small-signal model for the circuit of Fig. 4.4-6.

4.4 Current Mirrors

141

mirror is increased through the use of negative current . If i0 increao;es, then the current through M2 also increases. However, the mirroring action of Ml and M2 causes the current in Ml to increase.lfi1 is constant and if we assume there is some resistance from the gate of M3 (drain of Ml) to ground, then the gate voltage of M3 is decreased if the current i0 increases. The loop gain is essentially the product of Bml and the small-signal resistance seen from the drain of Ml to ground. It can be shown that the small-signal output resistance of the Wilson current source of Fig. 4.4-8 is (4.4-17) The output resistance of Fig. 4.4-8 is seen to be comparable with that of Fig. 4.4-6. Unfortunately, the behavior described above for the current mirrors or amplifier requires a nonzero voltage at the input and output before it is achieved. Consider the cascode current mirror of Fig. 4.4-6 from a large-signal viewpoint. This voltage at the input, designated as V~min), can be shown to depend on the value of i 1 as follows. Since v00 = 0 for both Ml and M3, these devices are always in saturation. Therefore, we may express V1(min) as 2i)' V1(min) = ( K:

12 [(L)Ii1 .

~~

] + (VTI + V73) + (~)' W 3 12

(4.4-18)

It is seen that for a given;, the only way to decrease V1(min) is to increase the WIL ratios of both Ml and M3. One must also that V13 will be larger due to the back-gate bias on M3. The techniques used to reduce VMlN at the output of the cascode current sink/source in Section 4.3 are not applicable here. We are also interesled in the voltage, VMJN, where M4 makes the transition from the nonsaturated region to the saturated regiQn. This voltage can be found from the relationship (4.4-19) or (4.4-20) Figure 4.4-8 Wilson cummt mirror.

M3

Ml

M2

142


which is when M4 is on the threshold between the two regions. Equation (4.4-20) can be used to obtain the value of VMIN as VMIN = V, - Vn =

K: 12 [(I. ~~ )'12 + (~)'12] Wl + (Vrt + Yr3 (21)'

Vr4)

(4.4·21)

For voltages above VMIN• the transistor M4 is in saturation and the output resistance should be that calculated in Eq. (4.4-16). Since the value of voltage across M2 is greater than necessary for saturation, the technique used to decrease VMIN in Section 4.3 can be used to decrease VMJN. Similar relationships can be developed for the Wilson current mirror or amplifier. Tf M3 Is saturated, then V1(min) is expressed as (4.4-22) For M3 to be saturated, VoUT must be greater than Votrr(sat) given as VoUT(sat) = VI - Vn

2J )1r.z [ ( ~ )'12 = ( IF w2 + (Lw33 )'11] + VT2

0

(4.4-23)

It is seen that both of these circuits require at least 2Vracross the input before they behave as described above. Larger WIL ratios will decrease V1(min) and V0 t)'l'(sat). An improvement on the Wilson current mirror can be developed by viewing from a clifferent perspective. Consider the Wilson current mirror redrawn in Fig. 4.4-9. Note that the resistance looking into the diode connection of M2 is rM2

Ml

r.u2

= ---"=-1 + gm2r.u2

(4.4-24)

Ml

(a)

(b)

Figure 4.4-9 (a) W'tbon current mkmr redrawn. (b) Wilson cu.rrent mirror modified to incre;!,se r""' at M2.

4.5 Current and Voltage References

143

Figure 4.4-10 Regulated cascode current mirror.

Ml

If the gate of M2 is tied to a bias voltage so that rM2 becomes

(4.4-25) then the expression for rwt is given as (4.4-26) (4.4-27) This new current mirror illustrated fully in Fig. 4.4-10 is called a regulated cascode [7] and it achieves an output resistance on the order of g! r~. Each of the current mirrors discussed above can be implemented using p-channel devices. The circuits perform in an identical manner and exhibit the same small-signal output resistance. The use of n-channel and p-channel current mirrors will be useful in de biasing of CMOS circuits.

CURRfNT RNO VULTRG£ RHEREICES An ideal current or voltage reference is independent of power supply and temperature. Many applications in analog circuits require such a building block, which provides a stable current or voltage. The large-signal current and voltage characteristics of an ideal current and voltage reference are shown in Fig. 4.5-l. These characteristics are identical to those of the ideal current and voltage source. The term reference is used when the current or voltage values have more precision and stability than ordinarily found in a source. A reference is typically dependent on the load connected to it. It will always be possible to use a buffer amplifier to isolate the reference from the load and maintain the high performance of the reference. ln the discussion that follows, it will be assumed that a high-performance voltage reference can be used to implement a high-performance current reference and vice versa.

144


Figure 4.5-l /-V cbaracteriatic~ of ideal current and voltage referencet>.

,...,

• A very crude voltage ·reference can be made from a voltage divider between the power supplies. ive or active componento, can be used as the divider elements. Figure 4.5-2 shows an example of each. Unfortunately, the value of VREF is directly proportional to the power supply. let us quantify this relationship by introducing the concept of sensitivity S. The sensitivity of VReP of Fig. 4.5-2(a) to V00 can be expressed as

s~·.. = (iiVRmiVRI!P) .,

(ilV00 /V00)

= Voo

(iiVRBP)

VREP

ilV00

(4.5-1)

Eq11ation (4,5-1) ~an be interpreted as follows; if the sensitivity is 1, then a 10% ~hangc in V01) will re.'>ult in a 10% change in VREF (which is undesirable for a voltage reference). It may also be shown that the sensitivity of VRBP of Fig. 4.5-2(b) with respect to V00 is unity (see

Problem 4.5-1). A simple way of obtaining a better voltage reference is to use an llCtive device as shown in Fig. 4.5-3. In Fig. 4.5-3(a), the substrate BIT bas been connected to the power supply through a resistance R. The voltage across the pn junction is given as VIU!F = VEB

= kT In (!._) q

I,

(4.5-2)

Figure 4.5-2 Vollage references using volrage divisiod. (a) Resistor implemencation. (b) Active device implemencation.

+

(a)

(b)


145

Figlu'e 4..5-3 (a) pn June lion voltage reference. (b} Increasing VR!lfl of (a) .

•

•

(b)

where I, is the junction-saturation current defined in Eq. (2.5-4). If VDD is much greater than VEB> then the current I is given as (4.5-3) Thus, the reference voltage_ of this circuit is given as vl!EF a!

kT (Voo)

(4.5-4)

-In q Rl,

The sensitivity of VIU!l' of Fig. 4.5-3(a) to V00 is shown to be 1

1

S~:;' = ln[VDd(Rl,)] = -ln-(l-IIJ-

(4.5-5)

Interestingly enough, since I is normally greater than I,. the sensitivity of VIU!l' of Fig. 4.5-3(a) is less than unity. For example, if I = 1 rnA and I, = 10-ls A, then Bq. (4.5-5) becomes 0.0362. Thus, a 10% change in V00 creates only a 0.362% change in VREF· Figure 4.5-3(b) shows a method of increasing the value of VREF in Fig. 4.5-3(a). The reference voltage of Fig. 4.5-3{b) can be written as (4.5-6) In order to find the value of VEB> it is necessary to assume that the transistor !SF (commonemitter current gain) is large and/or the resistance R1 + R2 is large. The larger VRHI' becomes

146


in Fig. 4.5-3(b), the more the current I beoomes a function of VRBP and eventually an iterative solution is necessary. The BIT of Fig. 4.5-3(a) may be replaced with aMOS enhancement device to achieve a voltage that is less dependent on V00 than Fig. 4.5-2(a) as shown in Fig. 4.5-4(a). VREFcan be found from Eq. (4.2-2), which gives Vas as

Vas= Ignoring channel length modulation,

v; REF

Vl(e'

Vr+~

(4.5-7)

is

= V __1_ + T (JR

f2(Vol> ~ Vr) (JR

V

+ _1_ /flf

(4.5-8)

= 2, and R is 100 kO, the values of Table 3.1-2 give a reference voltage of 1.281 V. The sensitivity of Fig. 4.5-4(a) can be found as

IfV00 = 5 V, WIL

5v,... ( v..., = I

1

+ (j (VREF -

Vr)R

)

(V~>o) VREF

(4.5-9)

Using the previous values gives a sensitivity of VRBP to Vol> of0.283. This sensitivity is not as good as the BJT because the logarithmic function is much less sensitive to its argument than

the square root The value of VREF of Fig. 4.5-4(a) can be increased using the technique employed for the BIT reference of Fig. 4.5-3(b), with the result shown in Fig. 4.5-4(b), where the reference voltage is given as (4.5-10) Figure 45-4 (a) MOS equivalent of the pn junction voltage reference. (b) Increasing VRI!I' of (a).

•

+

(I)

(b)


147

Figure 4.5-5 1-V characteristics of a breakdown diode.

•

••

• ••

•,

••

••

•• lu - • - . - - ........

Q

••

••

•

In the types of voltage references illustrated in Figs. 4.5-3 and 4.5-4, the designer can use geometry to adjust the value of VRI!I'.ln the BJT reference the geometric-dependent parameter is I, and for the MOS reference it is WIL The small-signal output resistance of these references is a measure of how dependent the reference will be on the load (see Problem 4.5-5). A voltage reference can be implemented using the breakdown phenomenon that occurs in the reverse-bias condition of a heavily doped pn junction discussed in Section 2.2. The symbol and current-voltage characteristics of the breakdown diode are shown in Fig. 4.5-5.

The breakdown in the reverse direction (v and i are defined for reverse bias in Fig. 4.5-S) occurs at a voltage BV. BV falls in the range of 6-8 V, depending on the doping concentrations of the n+ and p+ regions. The knee of the curve depends on the material parameters and should be very sharp. The small-signal output resistance in the breakdown region is low, typically 30-100 n. which makes an excellent voltage reference or voltage source. The temperature coefficient of the breakdown diode will vary with the value of breakdown voltage BV as seen in Fig. 4.5-6. Breakdown by the Zener mechanism has a negative temperature coefficient while the avalanche breakdown has a positive temperature coefficient. The breakdown voltage for typical CMOS technologies is around 6.5-7.5 v. which gives a temperature coefficient around +3 mV/°C. The breakdown diode can be used as a voltage reference by simply connecting it in series with a voltage-dropping element (resistor or active device) to V00 or Vss as illustrated in Fig. 4.5-7(a). The dotted load line on Fig. 4.5-5 mustrates the operation of the breakdown-diode Figure 4.5-6 Variation of the temperature coefficient of the breakdown diode as a funclion

6

E ' ~ 4 ~

l

tI -~+--~--!---JP'--:!--±--~t

Fo

of the breakdown voltage, BV. (By permission

from Jolm Wiley & Sons, Inc.)

·I

·2 ·3

Vf1

14


in Fig. 4.5-3(b), the more the current I becomes a function of VRBP and eventually an iterative solution is necessary. The BJT of Fig. 4.5-3(a) may be replaced with aMOS enhancement device to achieve a voltage that is less dependent on V00 than Fig. 4.5-2(a) as shown in Fig. 4.5-4(a). VRI!Pcan be found from Eq. (4.2-2), which gives Vas as Vas= Vr+

~

(4.5-7)

Ignoring channel length modulation. VRI!I' is

= V.

V.

__1_

+

{JR

T

JU;f

/2
{JR

+ _1_

(4.5-8)

(32/f

If V00 = S V, WIL = 2, and R is 100 ldl, the values of Table 3.1-2 give a reference voltage of 1.281 V. The sensitivity of Fig. 4.5-4(a) can be found as

~ sv:; =

(

I

1

+ fJ (VREF -

Vr)R

)(Voo) VRl!F

(4.5-9)

Using the previous values gives a sensitivity of V REF to V00 of 0.283. This sensitivity is not as good as the BIT because the logarithmic function is much less sensitive to its argument than the square root. The value of VRBP of Fig. 4.5-4(a) can be increased using the technique em· ployed for the BJT reference of Fig. 4.5-3(b), with the result shown in Fig. 4.5-4(b), where the reference voltage is given as

..

VRBF

= Vas ( l + R'Rt1.) Figure 4.5-4 (a) MOS equivalent of the pn junction voltage reference. (b) Increasing VREF of (a)•

•

+

(al

(b)


147

Figure 4.5-5 l-V characteristics of a breakdown diode .

• In the types of voltage references iUustra:ted in Figs. 4.5-3 and 4.5-4, the designer can use geometry to adjust the value of V!U!P. In the BJT reference the geometric-dependent parameter is I, and for the MOS reference it is WIL. The small-signal output resistance of these referen<:es is a measure of how dependent the reference wiU be on the load (see Problem 4.5-5). A voltage reference can be implemented using the breakdown phenomenon that occurs in the reverse-bias condition of a heavily doped pn junction discussed in Section 2.2. The symbol and current-voltage characteristics of the breakdown diode are shown in Fig. 4.5-5. The breakdown in the revel"lle direction (v and i are defined for reverse bias in Fig. 4.5-5) occurs at a voltage BV. BV falls in the range of 6-8 V, depending on the doping concentrations of the n+ and p + regions. The knee of the curve depends on the material parameters and should be very sharp. The small-signal output resistance in the breakdown region is low, typically 30-100 n, which makes an excellent voltage reference or voltage source. The temperature coefficient of the breakdown diode will vary with the value of breakdown voltage BV as seen in Fig. 4.5-6. Breakdown by the Zener mechanism has a negative temperature coefficient while the avalanche breakdown has a positive temperature coefficient. The breakdown voltage for typical CMOS technologies is around 6.5-7.5 V. which gives a temperature coeffi-

cient around +3m VI"C. The breakdown diode can be used as a voltage reference by simply connecting it in series ~,J'JQ/~~~~.,.........,....;.,.,.w.,~-w-~-·/,:U

---------'¥<"

4.5-7(a). The dotted load line on Fig. 4.5-5 illustrates the operation of the breakdown-diode 6

Figure 4.5-6 Variation of Lbe temperature

~

5

!

•

coefficient of the breakdown diode as a function of the breakdown voltage, BV. (By permission from John Wiley & Sons, loc.)

~"" l ~

l 1

'l ·• '"

Vs

148

ANALOG CMOS SUBCIRCUITS Figure 4.5-7 (a) BreakdoWII-diode voltage reference. (b) Small-signal model of (a).

lt>l

(ll)

voltage reference. If V00 orR should vary, little changeinBVwill reAult because of the steepness of the cwve in the breakdown region. The sensitivity of the breakdown-diode voltage reference can easily be found by replacing the circuit in Fig. 4.5-7(a) with its small-signal equivalent model. The resistor r, is equal to the inverse of the slope of Fig. 4.5-5 at the point Q. The sensitivity of VRBP to VDD can be expressed as

s~::,

(avREF) (VRBP Voo) itVnc

a

(Yrct·) (Von)=(-.!!..__) (Voo) VdJ BV '= + R BV

(4.5-11)

=

100 0, and R = 35 kO. Equation (4.5-11) gives Assume that V00 = 10 V, BV = 6.5 V. r~ the sensitivity of this breakdown-diode voltage reference as 0.0044. Thus, a 10% change in V00 would cause only a 0.044% change in VREI'· Other configurations of a voltage reference that use the breakdown diode are considered in the problems. We have noted in Figs. 4.5-3(a) and 4,5-4(a) that the sensitivity of the voltage across an active device is less than unity. If the voltage across the active device is used to create a current and this current is somehow used to provide the original current through the device, lhen a current or voltage will be obtained that is for all practical purposes independent of V00• This technique is called a VT referenced source. 1bis technique is also called a bootstrap reference. Figure 4.5-8(a) shows an example of this technique using all MOS devices. M3 and M4 cause the currents 11 and 12 to be equal./1 flows through Ml creating a voltage Vas 1.12 ftows through R creating a voltage 12R. Because these two voltages are connected together, an equilibrium point is established. Figure 4.5-S(b) illustrates how the equilibrium point is achieved. On this curve, 11 and 12 are plotted as a function of V. The intersection of these curves defines the equilibrium point indicated by Q. The equation describing this equilibrium point is given as _

I2R-

(2/L ) I

Vn

I

112

+ -,-

(4.5-12)

KNW1

This equation can be solved for 11 = 12 = Ia- giving (ignoring A,)

1 = 12 Q

=

Vn R

+ _l_ +.!. {J 1R.'-

R

f2Vn

+ _1_

\1 fJ1R tJiR'-

(4.5-13)


149

MS

M6

w Figure 4.5-8 (a) Threshold-referenced circuit. (b) I-V characteristics of (a), point is established.

w illustrating how the billli

To first order, neither 11 nor 12 changes as a function of VDO: thus, the sensitivity of Ia to VoD is essentially zero. A voltage reference can be achieved by mirroring 12 (= /Q) through M5 or M6 and using a resistor. Unfortunately, there are two possible equilibrium points on Fig. 4.5-S(b). One is at Q and the other is at the origin. In order to prevent the circuit from choosing the wrong equilibrium point, a startup circuit is necessary. The circuit within the dotted box in Fig. 4.5-S(a) functions as a startup circuit. If the circuit is at the undesired equilibrium point. then 11 and 12 are zero. However, M7 will provide a current in Ml that will cause the circuit to move to the equilibrium point at Q. As the circuit approaches the point Q, the source voltage of M7 increases, causing the current through M7 to decrease. At Q the current through M1 is essentially the current through M3. An alternate version of Fig. 4.5·8(a) that uses V8 £ to reference the voltage or current is shown in Fig. 4.5-9. It can be shown that the equilibrium point is defined by the relationship (4.5-14) This reference circuit also ha.~ two equilibrium points and a startup circuit similar to Fig. 4.5-B(a) is necessary. The reference circuil~ in Figs. 4.5-S(a) and 4.5-9 represent a very good method of implementing power-supply-independent references. Either circuit can be operated in the weak-threshold inversion in order to develop a low-power. low-supply-voltage reference. UnfortUnately, supply-independent references are not necessarily temperature independent because the pn junction and gate-source voltage drops are temperature dependent, as

150


Figure 4.5·9 Ba-miner voltage-referenced circuit.

noted in Section 2.5. The concept of fractional temperature coefficient (TCF), defined in Eq. (2.5-7), will be used to chlll"lK:terize the temperature dependence of voltage and current references. We see that TCF is related to the sensitivity as defined in Eq. (4.5-1) (4.5-15) where X= VRBF or /REF. Let us now consider the temperature characteristics of the simple pn junction of Fig. 4.5-3{a). H we assume that V00 is much greater than VREF, then Eq. (4.5-4) describes the reference voltage. Although V00 is independent of temperature, R is not and must be considered. The fractional temperature coefficient of Ibis voltage reference can be expressed using lhe results or Eq. (2.5-17) as (4.5-16) if vE = VIU!l'. Assuming a VREF of 0.6 V at room temperature, the TCF of the simple pn voltage reference is approximately -2500 ppmi"C. Figure 4.5-4(a) is the MOS equivalent of the simple pn junction voltage reference. The temperature dependence of VRBF of this circuit can be written as

_ dVREF

--=

dT

{Voo- YREF

a

+V 1+

2{JR

(1.5T _]_R dR) dT

1

Y2(3R (Voo- VRI!P)

(4.5-17)


151

CALCULATION OF THRESHOLD VOLTAGE REFERENCE CIRCUIT Calculate the temperature coefficient of !he circuit in Fig. 4.5-4{a), where WIL = 2, VDD = S V, and R = 100 kO, using the parameters ofThble 3.1-2. Resistor R is polysilicon and has a temperature coefficient of 1500 ppmf'C. Solution

Using Eq. (4.5-8),

+ ~UVvo -

., V 1 "Rl!F = T - {jR

v:

= 220 X =

10-6 X lo'

o7 - ..!._

REP

+ -1-2 {fR

= 22

/,_2<-s---o.-7}-+----,(=-I-=-)•2

22+-v

'

Vr)

{3R

fJB

22

22

VREF = 1.28] 1 dR

R ril'

= 1500 ppm/"C -a +

rvDD- VREI' (~-.!. dR)

dVREF " 2{jR T R ril' - = ------'-----:--'-----'dT 1+ ] V2{JR Wno - VREF)

x w- 3 + (s -

281

1. ( 1.5 - 1500 x wv 2(22) 300 --=-------=--....:.........:..._..,.....: ______ ....;...

-2 3

dVREP

•

1+

ril'

6)

l

v'2<22> <s - 1.2st>

dV~ =

-1.189

x

I0-3 vrc

The fractional temperature coefficient is given by

TC

F

1 dVREP VREI' ril'

=----

giving, for this example,

1 1.281

TCF = -1.189 X 10-3 ( --) "C- 1

= -928 ppm/"C

152


Unfortunately, the rc, of this example is not realistic because the values of (I and the reF of the resistor do not have the implied accuracy. The temperature characteristics of the breakdown diode were illustrated in Fig. 4.5-6. 'I}rpically, the temperature coefficient of the breakdown diode is positive. If the breakdown diode can be suitably combined with a negative temperature coefficient, then the possibility of temperature independence exist<~. Unfortunately, the temperature coefficient depends on the processing parameters and cannot be well defined, so this approach is not attractive. The bootstrap reference circuitofFig.4.5-8(a) has itscurrent/2 given by Eq. (4.5-l3).1fthe product of R andP is large, the Toftbe bootstrap reference circuit can be approximated as 1 dVr 1 dR -a 1 dR T=-----=---Vr dT R dT Vr R dT

(4.5-18)

CALCULATION OF BOOTSTRAP REFERENCE CIRCUIT

Calculate the temperature coefficient of the circuit in Fig. 4.5-8(a), where (W/L) 1 = 20, V00 = 5 V, and R = I00 k!l using the parameters ofTable 3. 1-2. Resistor R is polysilicon and has a temperature coefficient of 1500 ppmi"C. a = 2.3 X 10-3 V/°C,

lt1MI£.1,1 Using Eq. (4.5-13),

Vn

Ia

1

1 j2Vn

1

= h = R + p,Jf + R'V (3,R + MRZ

{J 1R = 220 X 10-.s X

lOS= 220

{J,Jf = 220 X 10-S X 1010 = 22

X

106

(-•-)2 220

r----~--.--:;

l _ 0.7 _ Q-

lOS

+ _1_

1 22

X

JO"

/2 X 0.7 105 \j 220

+

10 = 7.75 ILA

1 dR R dT = 1500 pprnfC TCF

= - 2 ·3O~ lO-l

- 1500 X Hl-6 oc-t

= -4.79 X 10- 3 •c-t =

-4790 ppm/"C

The temperature behavior of the base-emitter-referenced circuit of Fig. 4.5-9 is similar to that of the threshold-referenced circuit of Fig. 4.5-S(a). Equation (4.5-14) showed that / 2 is equal to V8111 divided by R. Thus, Eq. (4.5-18) above expresses the Tofthis reference if Vr is replaced by V8 e as follows: I dV 1 dR T C p = -811- - - - V811

dT

RD

Assuming V8 E of 0.6 V gives a TC,of -2333 ppmi"C.

(4.5-19)

4.6 Bandgap Reference

153

The voltage and current references presented in this section have the objective of providing a stable value of current with respect to changes in power supply and temperature. It was seen that while power-supply independence could thus be obtained, satisfactory temperature performance could not. To illustrate this conclusion, consider the accuracy requirement for a voltage reference for 8-bit accuracy. Maintaining this accuracy over a 10o•c change require.'! the TCF of the reference to be 11(256 X lOO"C) or 39 pprnJ•c.

G

BRNDGHP REFERENCE In this section we present a technique that results in references that have very little dependence on temperature and power supply. The bandgap reference [8-12] can generate references having a temperature coefficient on the order of 10 ppm/"C over the temperature range of 0-70 •c. The principle behind the bandgap reference is illustrated in Fig. 4.6-l. A voltage V8 e is generated from a pn-junction diode having a temperature coefficient of approximately -2.2 mvrc at room temperature. Also generated is a thermal voltage v, (= kT/q), which is proportional to absolute temperature (PTAT) and has a temperature coefficient of +0.085 mV/"C at room temperature. If the V, voltage is multiplied by a constant K and summed with the V8 e voltage, then the output voltage is given as

(4.6-1) Differentiating Eq. (4.6-1) with respect to temperature and using the temperature coefficients for V8 E and V, le!lds to a value of K that should theoretically give zero temperature dependence. In order to achieve the desired performance, it is necessary to develop the temperature dependence of V8 e in more detail One can see that since V8 e can have little dependence on the power supply (i.e., the bootstrapped references of Section 4.5), the power-supply dependence of the bandgap reference will be quite small.

,·-

V

kT q

v,

KV,

Figure 4.6-1 Gcneml principle of the bandgap reference.

154

ANALOG CMOS SUBCJRCUITS

To understand thoroughly how the bandgap reference works, we must first develop the temperature dependence of VB£· Consider the relationship for the collector-current density in a bipolar transistor,

qD,.n,., (Vs£) Jc=--exp -

w,

(4.6-2)

v,

where

lc = collector current density (A/m 2)

n"" = equilibrium concentration of electrons in the base D, == average diffusion constant for electrons

W8

= base width

The equilibrium concentration can be expressed as n~

n =~"' N,..

(4.6-3)

where (4.6-4) The tenn Dis a temperature-independent constant and Vao is the bandgap voltage (1.205 V). Combining Eqs. (4.6-2) through (4.6-4) results in the following equation for collector-current density:

(4.6-5)

= AT,-e:tp ( Vas-V, Voo)

(4.6-6)

In Eq. (4.6-6), the temperature-independent constants of Eq. (4.6-5) are combined into a single constant A The coefficient of temperature 'Y is slightly different from 3 due to the temper• ature dependence of D,. A relation for VBE can be developed from Eq. (4.6-6) and is given as

kT ( -lc) Vse=-ln q AT"

+ Vao

(4.6-7)

Now consider lc at a temperature T{l. leo= ATJ exp

[k~o
Vao)

J

(4.6-8)

4.6 Bandgap Reference

155

The ratio of Jc to J co is

Jc leo

=

(!_).,. To

exp [!(VsE- Vao _ Vsm- V00 )]

k

T

(4.6-9)

To

Equation (4.6-9) can be rearranged to get V8 e:

( T)

( T) "(kT (To) +-In kT (Jc) -

VaE= VG!I 1 - - + V8 lill +-ln To To q T

q

To

leo

(4.6-10)

lc

By taking the derivative ofEq. (4.6-10) at with respect to temperature (assuming that has a temperature dependence of 1""), the dependence of V8Eon temperature is clearly seen to be

(4.6-11) At 300 K the change of V8 ,. with respect to tempetature is approximately -2.2 mV?C. We have thus derived a suitable relationship for the V8 E term shown in Fig. 4.6-1. Now, it is also necessary to develop the relationship for AV8 ,. for two bipolar transistors having different current densitie.s. Using the relationship given in Eq. (4.6-7), a relationship for li.V8 E can be given as

kT (let)

A.VsE = Vs£1- VsE2 =-In q Ja.

(4.6-12)

Therefore,

aAVBE = V, In (let) iJT

T

(4.6-13)

la.

In order to achieve zero temperature coefficient at T0 , the variations of VBE and ll. V8 ,. as given in Eqs. (4.6-11) and (4.6-13) must add up to zero. This is expressed mathematically as

O K" (Vr
=

T0

(a - 'Y>VJO

T0

T0

0

(4.6-14)

where K" is a circuit constant adjusted to make Eq. (4.6-14) true. Define K = K" ln [10 /la) and substitute in Eq. (4.6-14) to get

0= K

(-v10_) + T0

V sliU -

To

vao + .:..: <...._--- rel="nofollow">

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Cmos Analog Circuit Design Holberg 144p2o

Overview 6h3y3j

More details h6z72

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